| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| H A D | dcn20_dccg.h | 122 #define DCCG_REG_FIELD_LIST(type) \ argument
123 type DPPCLK0_DTO_PHASE;\
124 type DPPCLK0_DTO_MODULO;\
125 type DPPCLK_DTO_ENABLE[6];\
126 type DPPCLK_DTO_DB_EN[6];\
127 type REFCLK_CLOCK_EN;\
128 type REFCLK_SRC_SEL;\
129 type DISPCLK_STEP_DELAY;\
130 type DISPCLK_STEP_SIZE;\
131 type DISPCLK_FREQ_RAMP_DONE;\
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| /linux/Documentation/netlink/specs/ |
| H A D | tc.yaml | 15 type: struct
20 type: u8
23 type: pad
27 type: s32
30 type: u32
33 type: u32
36 type: u32
40 type: flags
51 type: flags
61 type: enum
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| H A D | nl80211.yaml | 12 type: enum
172 type: flags
207 name: channel-type
208 type: enum
216 type: struct
220 type: u32
223 type: u32
226 type: flags
239 type: u32
242 type: string
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| H A D | rt-link.yaml | 14 type: flags
59 type: enum
70 type: struct
74 type: u8
77 type: struct
81 type: u8
84 type: pad
87 name: ifi-type
88 type: u16
91 type: s32
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| H A D | ovs_flow.yaml | 14 type: struct
20 type: u32
26 type: struct
30 type: u64
34 type: u64
38 type: struct
42 type: binary
47 type: binary
52 type: struct
56 type: u32
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| H A D | rt-neigh.yaml | 14 type: struct
18 type: u8
21 type: pad
25 type: s32
28 type: u16
32 type: u8
35 name: ndm-type
36 type: u8
37 enum: rtm-type
40 type: struct
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|
| H A D | ethtool.yaml | 15 name: udp-tunnel-type
17 type: enum
19 enum-cnt-name: __ethtool-udp-tunnel-type-cnt
23 type: enum
28 type: flags
43 type: enum
64 type: enum
96 name: phy-upstream-type
99 type: enum
104 type: enum
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| H A D | rt-route.yaml | 13 name: rtm-type
16 type: enum
32 type: struct
36 type: u8
39 type: u8
42 type: u8
45 type: u8
48 type: u8
51 type: u8
54 type: u8
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| H A D | nftables.yaml | 13 type: struct
17 type: u8
20 type: u8
24 type: u16
27 type: enum
67 type: enum
74 type: enum
83 name: object-type
84 type: enum
99 type: flags
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/ |
| H A D | dcn10_optc.h | 415 #define TG_REG_FIELD_LIST_DCN1_0(type) \ argument
416 type VSTARTUP_START;\
417 type VUPDATE_OFFSET;\
418 type VUPDATE_WIDTH;\
419 type VREADY_OFFSET;\
420 type OTG_BLANK_DATA_EN;\
421 type OTG_BLANK_DE_MODE;\
422 type OTG_CURRENT_BLANK_STATE;\
423 type OTG_MASTER_UPDATE_LOCK;\
424 type UPDATE_LOCK_STATUS;\
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| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| H A D | dcn10_stream_encoder.h | 355 #define SE_REG_FIELD_LIST_DCN1_0(type) \ argument
356 type AFMT_GENERIC_INDEX;\
357 type AFMT_GENERIC_HB0;\
358 type AFMT_GENERIC_HB1;\
359 type AFMT_GENERIC_HB2;\
360 type AFMT_GENERIC_HB3;\
361 type AFMT_GENERIC_LOCK_STATUS;\
362 type AFMT_GENERIC_CONFLICT;\
363 type AFMT_GENERIC_CONFLICT_CLR;\
364 type AFMT_GENERIC0_FRAME_UPDATE_PENDING;\
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| /linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/ |
| H A D | dcn30_dwb.h | 409 #define DWBC_REG_FIELD_LIST_DCN3_0(type) \ argument
410 type DWB_ENABLE;\
411 type DISPCLK_R_DWB_GATE_DIS;\
412 type DISPCLK_G_DWB_GATE_DIS;\
413 type DWB_TEST_CLK_SEL;\
414 type DWBSCL_LUT_MEM_PWR_FORCE;\
415 type DWBSCL_LUT_MEM_PWR_DIS;\
416 type DWBSCL_LUT_MEM_PWR_STATE;\
417 type DWBSCL_LB_MEM_PWR_FORCE;\
418 type DWBSCL_LB_MEM_PWR_DIS;\
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| H A D | dcn20_dsc.h | 269 #define DSC_FIELD_LIST_DCN20(type)\ argument
270 type DSC_CLOCK_EN; \
271 type DSC_DISPCLK_R_GATE_DIS; \
272 type DSC_DSCCLK_R_GATE_DIS; \
273 type DSC_DBG_EN; \
274 type DSC_TEST_CLOCK_MUX_SEL; \
275 type ICH_RESET_AT_END_OF_LINE; \
276 type NUMBER_OF_SLICES_PER_LINE; \
277 type ALTERNATE_ICH_ENCODING_EN; \
278 type NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION; \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/ |
| H A D | dcn20_mmhubbub.h | 252 #define MCIF_WB_REG_FIELD_LIST_DCN2_0(type) \ argument
253 type MCIF_WB_BUFMGR_ENABLE;\
254 type MCIF_WB_BUFMGR_SW_INT_EN;\
255 type MCIF_WB_BUFMGR_SW_INT_ACK;\
256 type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\
257 type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\
258 type MCIF_WB_BUFMGR_SW_LOCK;\
259 type MCIF_WB_P_VMID;\
260 type MCIF_WB_BUF_ADDR_FENCE_EN;\
261 type MCIF_WB_BUFMGR_CUR_LINE_R;\
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| /linux/drivers/gpu/drm/msm/registers/display/ |
| H A D | dsi.xml | 76 <bitfield name="CMD_DMA_DONE" pos="0" type="boolean"/>
77 <bitfield name="MASK_CMD_DMA_DONE" pos="1" type="boolean"/>
78 <bitfield name="CMD_MDP_DONE" pos="8" type="boolean"/>
79 <bitfield name="MASK_CMD_MDP_DONE" pos="9" type="boolean"/>
80 <bitfield name="VIDEO_DONE" pos="16" type="boolean"/>
81 <bitfield name="MASK_VIDEO_DONE" pos="17" type="boolean"/>
82 <bitfield name="BTA_DONE" pos="20" type="boolean"/>
83 <bitfield name="MASK_BTA_DONE" pos="21" type="boolean"/>
84 <bitfield name="ERROR" pos="24" type="boolean"/>
85 <bitfield name="MASK_ERROR" pos="25" type="boolean"/>
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| H A D | mdp5.xml | 95 <bitfield name="WB_0_DONE" pos="0" type="boolean"/>
96 <bitfield name="WB_1_DONE" pos="1" type="boolean"/>
97 <bitfield name="WB_2_DONE" pos="4" type="boolean"/>
98 <bitfield name="PING_PONG_0_DONE" pos="8" type="boolean"/>
99 <bitfield name="PING_PONG_1_DONE" pos="9" type="boolean"/>
100 <bitfield name="PING_PONG_2_DONE" pos="10" type="boolean"/>
101 <bitfield name="PING_PONG_3_DONE" pos="11" type="boolean"/>
102 <bitfield name="PING_PONG_0_RD_PTR" pos="12" type="boolean"/>
103 <bitfield name="PING_PONG_1_RD_PTR" pos="13" type="boolean"/>
104 <bitfield name="PING_PONG_2_RD_PTR" pos="14" type="boolean"/>
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dwb.h | 202 #define DWBC_REG_FIELD_LIST_DCN2_0(type) \ argument
203 type WB_ENABLE;\
204 type DISPCLK_R_WB_GATE_DIS;\
205 type DISPCLK_G_WB_GATE_DIS;\
206 type DISPCLK_G_WBSCL_GATE_DIS;\
207 type WB_TEST_CLK_SEL;\
208 type WB_LB_LS_DIS;\
209 type WB_LB_SD_DIS;\
210 type WB_LUT_LS_DIS;\
211 type WBSCL_LB_MEM_PWR_MODE_SEL;\
[all …]
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| /linux/drivers/net/ethernet/microchip/vcap/ |
| H A D | vcap_model_kunit.c | 19 .type = VCAP_FIELD_U32,
24 .type = VCAP_FIELD_BIT,
29 .type = VCAP_FIELD_U32,
34 .type = VCAP_FIELD_U32,
39 .type = VCAP_FIELD_U32,
44 .type = VCAP_FIELD_U32,
49 .type = VCAP_FIELD_BIT,
54 .type = VCAP_FIELD_U32,
59 .type = VCAP_FIELD_U32,
64 .type = VCAP_FIELD_U32,
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| H A D | dcn10_hubp.h | 473 #define DCN_HUBP_REG_FIELD_BASE_LIST(type) \ argument
474 type HUBP_BLANK_EN;\
475 type HUBP_DISABLE;\
476 type HUBP_TTU_DISABLE;\
477 type HUBP_NO_OUTSTANDING_REQ;\
478 type HUBP_VTG_SEL;\
479 type HUBP_UNDERFLOW_STATUS;\
480 type HUBP_UNDERFLOW_CLEAR;\
481 type HUBP_IN_BLANK;\
482 type NUM_PIPES;\
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|
| /linux/Documentation/netlink/ |
| H A D | netlink-raw.yaml | 10 type: string
13 type: string
16 type: integer
19 type: [ string, integer ]
26 type: object
32 type: string
34 type: string
41 type: integer
45 type: string
49 type: string
[all …]
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| H A D | genetlink-c.yaml | 10 type: integer
13 type: [ string, integer ]
17 # literal int, const name, or limit based on fixed-width type
19 type: [ string, integer ]
26 type: object
32 type: string
34 type: string
40 type: string
44 type: string
47 type: string
[all …]
|
| /linux/drivers/net/ethernet/microchip/sparx5/ |
| H A D | sparx5_vcap_ag_api.c | 19 .type = VCAP_FIELD_BIT,
24 .type = VCAP_FIELD_BIT,
29 .type = VCAP_FIELD_U32,
34 .type = VCAP_FIELD_U32,
39 .type = VCAP_FIELD_U32,
44 .type = VCAP_FIELD_U72,
49 .type = VCAP_FIELD_BIT,
54 .type = VCAP_FIELD_BIT,
59 .type = VCAP_FIELD_U32,
64 .type = VCAP_FIELD_U32,
[all …]
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| /linux/drivers/net/ethernet/microchip/sparx5/lan969x/ |
| H A D | lan969x_vcap_ag_api.c | 18 .type = VCAP_FIELD_BIT,
23 .type = VCAP_FIELD_BIT,
28 .type = VCAP_FIELD_U32,
33 .type = VCAP_FIELD_U32,
38 .type = VCAP_FIELD_U32,
43 .type = VCAP_FIELD_U72,
48 .type = VCAP_FIELD_BIT,
53 .type = VCAP_FIELD_BIT,
58 .type = VCAP_FIELD_U32,
63 .type = VCAP_FIELD_U32,
[all …]
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| /linux/tools/testing/selftests/drivers/net/netdevsim/ |
| H A D | hw_stats_l3.sh | 85 local type=$1; shift
89 echo $ifindex > $(DEBUGFS_DIR $instance)/hwstats/$type/$action
127 $IP link add name dummy1 type dummy
147 local type=$1; shift
156 local type=$1; shift
158 [[ $(netdev_hwstats_used $netdev $type) == "true" ]]
164 local type=$1; shift
166 [[ $(netdev_hwstats_used $netdev $type) == "false" ]]
172 local type=$1; shift
175 jq ".[].info.${type}_stats.request"
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|
| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| H A D | dcn20_hubp.h | 185 #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ argument
186 DCN_HUBP_REG_FIELD_BASE_LIST(type); \
187 type DMDATA_ADDRESS_HIGH;\
188 type DMDATA_MODE;\
189 type DMDATA_UPDATED;\
190 type DMDATA_REPEAT;\
191 type DMDATA_SIZE;\
192 type DMDATA_SW_UPDATED;\
193 type DMDATA_SW_REPEAT;\
194 type DMDATA_SW_SIZE;\
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