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Searched full:trapping (Results 1 – 11 of 11) sorted by relevance

/qemu/docs/devel/
H A Duefi-vars.rst23 serializing the requests to a shared buffer, then trapping into SMM
/qemu/target/arm/tcg/
H A Dop_helper.c138 * to get the usual non-trapping division behaviour (result of 0) in handle_possible_div0_trap()
345 /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it in check_wfx_trap()
356 /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */ in check_wfx_trap()
H A Dhflags.c23 * should be trapping on SVC instructions. Only AArch64 can in fgt_svc()
H A Dsve_helper.c6223 /* Trapping mte check for the first-fault element. */ in sve_ldnfff1_r()
/qemu/target/arm/
H A Dcpregs.h135 * identically to the normal one, other than FGT trapping handling.)
678 * the FGT system only allows trapping of writes, not reads.
1154 * trapping rule, so we will need to add an ARM_CP_* flag to indicate in arm_cpreg_traps_in_nv()
H A Ddebug_helper.c980 * with trapping to prevent spurious SIGILLs if the guest OS does
H A Dhelper.c884 * trapping to EL2 or EL3 for other accesses. in pmreg_access()
9376 * fine-grained trapping. Add the NXS insn here and in define_one_arm_cp_reg_with_opaque()
/qemu/include/hw/xen/interface/arch-x86/
H A Dxen.h350 * Prefix forces emulation of some non-trapping instructions.
/qemu/target/m68k/
H A Dcpu.c152 * trapping them as unimplemented data types, allowing efficient conversion in m68k_cpu_reset_hold()
/qemu/target/riscv/
H A Dcpu_helper.c2142 /* Trapping to M mode, virt is disabled */ in riscv_do_nmi()
2402 /* Trapping to M mode, virt is disabled */ in riscv_cpu_do_interrupt()
/qemu/fpu/
H A Dsoftfloat.c104 * and trapping on every FP exception is not fast nor pleasant to work with.