| /linux/drivers/gpu/drm/tegra/ |
| H A D | mipi-phy.c | 16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
24 timing->clktermen = 0; in mipi_dphy_timing_get_default()
25 timing->clktrail = 80; in mipi_dphy_timing_get_default()
26 timing->clkzero = 260; in mipi_dphy_timing_get_default()
27 timing->dtermen = 0; in mipi_dphy_timing_get_default()
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| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra124-emc.c | 48 * When we change the timing to a timing with a parent that has the same
50 * timing that has a different clock source.
120 struct emc_timing *timing = NULL; in emc_determine_rate() local
136 timing = tegra->timings + i; in emc_determine_rate()
138 if (timing->rate < req->rate && i != t - 1) in emc_determine_rate()
141 if (timing->rate > req->max_rate) { in emc_determine_rate()
147 if (timing->rate < req->min_rate) in emc_determine_rate()
150 req->rate = timing->rate; in emc_determine_rate()
154 if (timing) { in emc_determine_rate()
155 req->rate = timing->rate; in emc_determine_rate()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_validation.c | 27 * This file owns timing validation against various link limitations. (ex.
38 static uint32_t get_tmds_output_pixel_clock_100hz(const struct dc_crtc_timing *timing) in get_tmds_output_pixel_clock_100hz() argument
41 uint32_t pxl_clk = timing->pix_clk_100hz; in get_tmds_output_pixel_clock_100hz()
43 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) in get_tmds_output_pixel_clock_100hz()
45 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) in get_tmds_output_pixel_clock_100hz()
48 if (timing->display_color_depth == COLOR_DEPTH_101010) in get_tmds_output_pixel_clock_100hz()
50 else if (timing->display_color_depth == COLOR_DEPTH_121212) in get_tmds_output_pixel_clock_100hz()
57 const struct dc_crtc_timing *timing, in dp_active_dongle_validate_timing() argument
66 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) in dp_active_dongle_validate_timing()
77 switch (timing->pixel_encoding) { in dp_active_dongle_validate_timing()
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| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_encoder_phys_vid.c | 46 struct dpu_hw_intf_timing_params *timing) in drm_mode_to_intf_timing_params() argument
48 memset(timing, 0, sizeof(*timing)); in drm_mode_to_intf_timing_params()
75 timing->width = mode->hdisplay; /* active width */ in drm_mode_to_intf_timing_params()
76 timing->height = mode->vdisplay; /* active height */ in drm_mode_to_intf_timing_params()
77 timing->xres = timing->width; in drm_mode_to_intf_timing_params()
78 timing->yres = timing->height; in drm_mode_to_intf_timing_params()
79 timing->h_back_porch = mode->htotal - mode->hsync_end; in drm_mode_to_intf_timing_params()
80 timing->h_front_porch = mode->hsync_start - mode->hdisplay; in drm_mode_to_intf_timing_params()
81 timing->v_back_porch = mode->vtotal - mode->vsync_end; in drm_mode_to_intf_timing_params()
82 timing->v_front_porch = mode->vsync_start - mode->vdisplay; in drm_mode_to_intf_timing_params()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| H A D | timing.c | 26 #include <subdev/bios/timing.h>
33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
51 return timing; in nvbios_timingTe()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_translation_helper.c | 79 max_hw_v_total -= stream->timing.v_front_porch + 1; in calc_max_hardware_v_total()
85 static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cfg *timing, in populate_dml21_timing_config_from_stream_state() argument
93 …timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_… in populate_dml21_timing_config_from_stream_state()
94 …timing->v_active = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.… in populate_dml21_timing_config_from_stream_state()
95 timing->h_front_porch = stream->timing.h_front_porch; in populate_dml21_timing_config_from_stream_state()
96 timing->v_front_porch = stream->timing.v_front_porch; in populate_dml21_timing_config_from_stream_state()
97 timing->pixel_clock_khz = stream->timing.pix_clk_100hz / 10; in populate_dml21_timing_config_from_stream_state()
99 timing->pixel_clock_khz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz / 10; in populate_dml21_timing_config_from_stream_state()
100 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) in populate_dml21_timing_config_from_stream_state()
101 timing->pixel_clock_khz *= 2; in populate_dml21_timing_config_from_stream_state()
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| /linux/drivers/video/fbdev/ |
| H A D | gbefb.c | 38 struct gbe_timing_info timing; member
411 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) in gbefb_setup_flatpanel() argument
417 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
419 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
427 timing->pll_m = 4; in gbefb_setup_flatpanel()
428 timing->pll_n = 1; in gbefb_setup_flatpanel()
429 timing->pll_p = 0; in gbefb_setup_flatpanel()
456 struct gbe_timing_info *timing) in compute_gbe_timing() argument
467 /* Determine valid resolution and timing in compute_gbe_timing()
503 /* set video timing information */ in compute_gbe_timing()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/ |
| H A D | dcn201_optc.c | 70 const struct dc_crtc_timing *timing) in optc201_validate_timing() argument
77 ASSERT(timing != NULL); in optc201_validate_timing()
79 v_blank = (timing->v_total - timing->v_addressable - in optc201_validate_timing()
80 timing->v_border_top - timing->v_border_bottom); in optc201_validate_timing()
82 h_blank = (timing->h_total - timing->h_addressable - in optc201_validate_timing()
83 timing->h_border_right - in optc201_validate_timing()
84 timing->h_border_left); in optc201_validate_timing()
86 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && in optc201_validate_timing()
87 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && in optc201_validate_timing()
88 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && in optc201_validate_timing()
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| /linux/drivers/memory/tegra/ |
| H A D | tegra124-emc.c | 516 /* Timing change sequence functions */
539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
577 struct emc_timing *timing = NULL; in tegra124_emc_find_timing() local
582 timing = &emc->timings[i]; in tegra124_emc_find_timing()
587 if (!timing) { in tegra124_emc_find_timing()
588 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra124_emc_find_timing()
592 return timing; in tegra124_emc_find_timing()
598 struct emc_timing *timing = tegra124_emc_find_timing(emc, rate); in tegra124_emc_prepare_timing_change() local
606 if (!timing) in tegra124_emc_prepare_timing_change()
609 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1)) in tegra124_emc_prepare_timing_change()
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| H A D | tegra30-emc.c | 409 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
440 struct emc_timing *timing = NULL; in emc_find_timing() local
445 timing = &emc->timings[i]; in emc_find_timing()
450 if (!timing) { in emc_find_timing()
451 dev_err(emc->dev, "no timing for rate %lu\n", rate); in emc_find_timing()
455 return timing; in emc_find_timing()
458 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing, in emc_dqs_preset() argument
464 if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) { in emc_dqs_preset()
475 if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) { in emc_dqs_preset()
486 if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) { in emc_dqs_preset()
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| /linux/drivers/video/fbdev/via/ |
| H A D | via_modesetting.c | 18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
27 raw.hor_sync_end = timing->hor_sync_end / 8; in via_set_primary_timing()
28 raw.ver_total = timing->ver_total - 2; in via_set_primary_timing()
29 raw.ver_addr = timing->ver_addr - 1; in via_set_primary_timing()
30 raw.ver_blank_start = timing->ver_blank_start - 1; in via_set_primary_timing()
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| /linux/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy_20nm.c | 11 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_20nm_dphy_set_timing()
17 writel(DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail), in dsi_20nm_dphy_set_timing()
19 writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare), in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
24 writel(DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), in dsi_20nm_dphy_set_timing()
26 writel(DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero), in dsi_20nm_dphy_set_timing()
28 writel(DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare), in dsi_20nm_dphy_set_timing()
30 writel(DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail), in dsi_20nm_dphy_set_timing()
32 writel(DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst), in dsi_20nm_dphy_set_timing()
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| H A D | dce110_timing_generator_v.c | 45 * DCE11 Timing Generator Implementation
243 const struct dc_crtc_timing *timing) in dce110_timing_generator_v_program_blanking() argument
245 uint32_t vsync_offset = timing->v_border_bottom + in dce110_timing_generator_v_program_blanking()
246 timing->v_front_porch; in dce110_timing_generator_v_program_blanking()
247 uint32_t v_sync_start = timing->v_addressable + vsync_offset; in dce110_timing_generator_v_program_blanking()
249 uint32_t hsync_offset = timing->h_border_right + in dce110_timing_generator_v_program_blanking()
250 timing->h_front_porch; in dce110_timing_generator_v_program_blanking()
251 uint32_t h_sync_start = timing->h_addressable + hsync_offset; in dce110_timing_generator_v_program_blanking()
262 timing->h_total - 1, in dce110_timing_generator_v_program_blanking()
271 timing->v_total - 1, in dce110_timing_generator_v_program_blanking()
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| /linux/drivers/media/rc/img-ir/ |
| H A D | img-ir-hw.h | 22 /* Timing information */
53 * struct img_ir_timing_range - range of timing values
54 * @min: Minimum timing value
55 * @max: Maximum timing value (if < @min, this will be set to @min during
65 * struct img_ir_symbol_timing - timing data for a symbol
66 * @pulse: Timing range for the length of the pulse in this symbol
67 * @space: Timing range for the length of the space in this symbol
75 * struct img_ir_free_timing - timing data for free time symbol
88 * struct img_ir_timings - Timing values.
89 * @ldr: Leader symbol timing data
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| /linux/drivers/gpu/drm/sti/ |
| H A D | sti_awg_utils.c | 122 struct awg_timing *timing) in awg_generate_line_signal() argument
127 if (timing->trailing_pixels > 0) { in awg_generate_line_signal()
129 val = timing->blanking_level; in awg_generate_line_signal()
132 val = timing->trailing_pixels - 1 + AWG_DELAY; in awg_generate_line_signal()
137 val = timing->blanking_level; in awg_generate_line_signal()
138 ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, in awg_generate_line_signal()
141 if (timing->blanking_pixels > 0) { in awg_generate_line_signal()
143 val = timing->active_pixels - 1; in awg_generate_line_signal()
147 val = timing->blanking_level; in awg_generate_line_signal()
156 struct awg_timing *timing) in sti_awg_generate_code_data_enable_mode() argument
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | ramnv50.c | 34 #include <subdev/bios/timing.h>
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
98 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
109 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in nv50_ram_timing_calc()
110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
114 timing[2] = (T(CWL) - 1) << 24 | in nv50_ram_timing_calc()
118 timing[3] = (unkt3b - 2 + T(CL)) << 24 | in nv50_ram_timing_calc()
122 timing[4] = (cur4 & 0xffff0000) | in nv50_ram_timing_calc()
125 timing[5] = T(RFC) << 24 | in nv50_ram_timing_calc()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 217 if (pipe->stream->timing.v_addressable != pipe->stream->dst.height || in dcn32_is_center_timing()
218 pipe->stream->timing.v_addressable != pipe->stream->src.height) { in dcn32_is_center_timing()
223 if (pipe->stream->timing.v_addressable != pipe->plane_state->dst_rect.height && in dcn32_is_center_timing()
224 pipe->stream->timing.v_addressable != pipe->plane_state->src_rect.height) { in dcn32_is_center_timing()
265 …if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 19… in override_det_for_subvp()
278 …if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 19… in override_det_for_subvp()
419 * Scaling factor for v_blank stretch calculations considering timing in
430 struct dc_crtc_timing *timing = NULL; in get_frame_rate_at_max_stretch_100hz() local
444 timing = &fpo_candidate_stream->timing; in get_frame_rate_at_max_stretch_100hz()
445 if (timing == NULL) in get_frame_rate_at_max_stretch_100hz()
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | sdhci-am654.yaml | 61 description: Output tap delay for SD/MMC legacy timing
67 description: Output tap delay for MMC high speed timing
73 description: Output tap delay for SD high speed timing
79 description: Output tap delay for SD UHS SDR12 timing
85 description: Output tap delay for SD UHS SDR25 timing
91 description: Output tap delay for SD UHS SDR50 timing
97 description: Output tap delay for SD UHS SDR104 timing
103 description: Output tap delay for SD UHS DDR50 timing
109 description: Output tap delay for eMMC DDR52 timing
115 description: Output tap delay for eMMC HS200 timing
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| /linux/drivers/ata/ |
| H A D | pata_triflex.c | 62 * triflex_load_timing - timing configuration
76 u32 timing = 0; in triflex_load_timing() local
88 timing = 0x0103;break; in triflex_load_timing()
90 timing = 0x0203;break; in triflex_load_timing()
92 timing = 0x0808;break; in triflex_load_timing()
96 timing = 0x0F0F;break; in triflex_load_timing()
98 timing = 0x0202;break; in triflex_load_timing()
100 timing = 0x0204;break; in triflex_load_timing()
102 timing = 0x0404;break; in triflex_load_timing()
104 timing = 0x0508;break; in triflex_load_timing()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_mall_phantom.c | 71 mall_alloc_height_blk_aligned = (pipe->stream->timing.v_addressable - 1 + mblk_height - 1) / in dml2_helper_calculate_num_ways_for_subvp()
247 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + in assign_subvp_pipe()
248 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) in assign_subvp_pipe()
249 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); in assign_subvp_pipe()
267 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total / in assign_subvp_pipe()
268 (double)(stream->timing.pix_clk_100hz * 100)) * 1000000; in assign_subvp_pipe()
378 microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) + in subvp_subvp_schedulable()
379 phantom->timing.v_addressable; in subvp_subvp_schedulable()
382 time_us = (microschedule_lines * phantom->timing.h_total) / in subvp_subvp_schedulable()
383 (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 + in subvp_subvp_schedulable()
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| /linux/drivers/leds/ |
| H A D | leds-expresswire.c | 20 fsleep(props->timing.poweroff_us); in expresswire_power_off()
31 udelay(props->timing.detect_delay_us); in expresswire_enable()
33 udelay(props->timing.detect_us); in expresswire_enable()
43 udelay(props->timing.data_start_us); in expresswire_start()
49 udelay(props->timing.end_of_data_low_us); in expresswire_end()
51 udelay(props->timing.end_of_data_high_us); in expresswire_end()
58 udelay(props->timing.short_bitset_us); in expresswire_set_bit()
60 udelay(props->timing.long_bitset_us); in expresswire_set_bit()
63 udelay(props->timing.long_bitset_us); in expresswire_set_bit()
65 udelay(props->timing.short_bitset_us); in expresswire_set_bit()
|
| /linux/Documentation/driver-api/memory-devices/ |
| H A D | ti-gpmc.rst | 20 GPMC generic timing calculation:
29 generic timing routine was developed to achieve above requirements.
37 happen that timing as specified by peripheral datasheet is not present
38 in timing structure, in this scenario, try to correlate peripheral
39 timing to the one available. If that doesn't work, try to add a new
40 field as required by peripheral, educate generic timing routine to
45 Generic timing routine has been verified to work properly on
48 A word of caution: generic timing routine has been developed based
50 custom timing routines, a kind of reverse engineering without
52 in mainline having custom timing routine) and by simulation.
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| /linux/drivers/gpu/drm/amd/display/dc/dce120/ |
| H A D | dce120_timing_generator.c | 100 /* determine if given timing can be supported by TG */
103 const struct dc_crtc_timing *timing, in dce120_timing_generator_validate_timing() argument
106 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; in dce120_timing_generator_validate_timing()
108 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
109 timing->v_border_top - timing->v_border_bottom) * in dce120_timing_generator_validate_timing()
115 timing, in dce120_timing_generator_validate_timing()
121 timing->h_sync_width < tg110->min_h_sync_width || in dce120_timing_generator_validate_timing()
122 timing->v_sync_width < tg110->min_v_sync_width) in dce120_timing_generator_validate_timing()
129 const struct dc_crtc_timing *timing) in dce120_tg_validate_timing() argument
131 return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE); in dce120_tg_validate_timing()
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| /linux/drivers/media/i2c/ |
| H A D | bt819.c | 60 struct timing { struct
70 static struct timing timing_data[] = { argument
164 0x16, 0x07, /* 0x16 Video Timing Polarity in bt819_init()
175 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; in bt819_init() local
178 (((timing->vdelay >> 8) & 0x03) << 6) | in bt819_init()
179 (((timing->vactive >> 8) & 0x03) << 4) | in bt819_init()
180 (((timing->hdelay >> 8) & 0x03) << 2) | in bt819_init()
181 ((timing->hactive >> 8) & 0x03); in bt819_init()
182 init[0x04 * 2 - 1] = timing->vdelay & 0xff; in bt819_init()
183 init[0x05 * 2 - 1] = timing->vactive & 0xff; in bt819_init()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/ |
| H A D | dcn10_optc.c | 50 * @timing: Timing parameters used to configure DCN blocks.
52 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) in apply_front_porch_workaround() argument
54 if (timing->flags.INTERLACE == 1) { in apply_front_porch_workaround()
55 if (timing->v_front_porch < 2) in apply_front_porch_workaround()
56 timing->v_front_porch = 2; in apply_front_porch_workaround()
58 if (timing->v_front_porch < 1) in apply_front_porch_workaround()
59 timing->v_front_porch = 1; in apply_front_porch_workaround()
140 * optc1_program_timing() - used by mode timing set Program
141 * CRTC Timing Registers - OTG_H_*,
146 * @dc_crtc_timing: Timing parameters used to configure DCN blocks.
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