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/linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
H A D	tlb.json	4 …"BriefDescription": "This event counts operations that cause a TLB refill of the L1I TLB. See L1I_… 8 …"BriefDescription": "This event counts operations that cause a TLB refill of the L1D TLB. See L1D_… 12 …"BriefDescription": "This event counts operations that cause a TLB access to the L1D TLB. See L1D_… 16 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I TLB. See L1I_… 20 …"BriefDescription": "This event counts operations that cause a TLB refill of the L2D TLB. See L2D_… 24 …"BriefDescription": "This event counts operations that cause a TLB access to the L2D TLB. See L2D_… 37 … "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 4KB page." 42 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 64KB page." 47 … "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 2MB page." 52 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 32MB page." [all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	memory.json	11 "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.", 16 …"PublicDescription": "Counts the number of misaligned load uops that are 4K page splits. Available… 21 "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.", 26 …"PublicDescription": "Counts the number of misaligned store uops that are 4K page splits. Availabl… 31 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 37 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 42 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 48 …"PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIS… 53 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 59 …"PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIS… [all …]
H A D	cache.json	7 …that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly… 20 …"BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue… 24 …"PublicDescription": "Counts the number of demand and prefetch transactions that the External Queu… 36 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 40 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d… 45 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a p… 49 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front … 54 …"BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Cou… 58 …"PublicDescription": "Counts the number of L2 Cache accesses that miss the L2 and get BBL reject … 63 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o… [all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	memory.json	11 "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.", 16 …"PublicDescription": "Counts the number of misaligned load uops that are 4K page splits. Available… 21 "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.", 26 …"PublicDescription": "Counts the number of misaligned store uops that are 4K page splits. Availabl… 31 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 37 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 42 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 48 …"PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIS… 53 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 59 …"PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIS… [all …]
H A D	cache.json	7 …that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly… 20 …"BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue… 24 …"PublicDescription": "Counts the number of demand and prefetch transactions that the External Queu… 36 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 40 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d… 45 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a p… 49 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front … 54 …"BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Cou… 58 …"PublicDescription": "Counts the number of L2 Cache accesses that miss the L2 and get BBL reject … 63 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o… [all …]
/linux/include/media/
H A D	v4l2-ioctl.h	25 * @vidioc_querycap: pointer to the function that implements 27 * @vidioc_enum_fmt_vid_cap: pointer to the function that implements 30 * @vidioc_enum_fmt_vid_overlay: pointer to the function that implements 33 * @vidioc_enum_fmt_vid_out: pointer to the function that implements 36 * @vidioc_enum_fmt_sdr_cap: pointer to the function that implements 39 * @vidioc_enum_fmt_sdr_out: pointer to the function that implements 42 * @vidioc_enum_fmt_meta_cap: pointer to the function that implements 45 * @vidioc_enum_fmt_meta_out: pointer to the function that implements 48 * @vidioc_g_fmt_vid_cap: pointer to the function that implements 51 * @vidioc_g_fmt_vid_overlay: pointer to the function that implements [all …]
/linux/Documentation/filesystems/
H A D	propagate_umount.txt	5 that set - anything with the same mountpoint as one of the removed 6 mounts and with parent that would receive events from the parent of that 16 2) A set S is non-revealing if all locked mounts that belong to S have 17 parents that also belong to S. 27 extend that set. The original set is a full subtree and its root is 28 unlocked; what matters is that it's closed and non-revealing. 30 of that set, but only on top of stacks of root-overmounting elements 32 stack is attached to a mount that will survive. NOTE: doing that 35 will immediately remedy that - it may keep unmounted element attached 40 doing that pretty much immediately after the call of propagate_umount(). [all …]
H A D	path-lookup.rst	22 exploration is needed to discover, is that it is complex. There are 23 many rules, special cases, and implementation alternatives that all 26 tool that we will make extensive use of is "divide and conquer". For 41 of elements: "slashes" that are sequences of one or more "``/``" 42 characters, and "components" that are sequences of one or more 43 non-"``/``" characters. These form two kinds of paths. Those that 52 component, but that isn't always accurate: a pathname can lack both 62 it must identify a directory that already exists, otherwise an error 68 pathname that is just slashes have a final component. If it does 75 tempting to consider that to have an empty final component. In many [all …]
H A D	directory-locking.rst	12 that "inode pointer" order in the following. 37 * check that the source is not a directory 40 5. rename that is _not_ cross-directory. Locking rules: 47 * take the locks that need to be taken (exclusive), in inode pointer order 48 if need to take both (that can happen only when both source and target 51 allowed only with RENAME_EXCHANGE, and that won't be removing the target). 60 * verify that the source is not a descendent of the target and 65 The rules above obviously guarantee that all directories that are going 78 that's not a problem, but there is a nasty twist - what should we do 79 when one growing tree reaches the root of another? That can happen in [all …]
/linux/drivers/gpu/drm/xe/
H A D	xe_gt_sriov_pf_control_types.h	16 * @XE_GT_SRIOV_STATE_WIP: indicates that some operations are in progress. 17 * @XE_GT_SRIOV_STATE_FLR_WIP: indicates that a VF FLR is in progress. 18 * @XE_GT_SRIOV_STATE_FLR_SEND_START: indicates that the PF wants to send a FLR START command. 19 * @XE_GT_SRIOV_STATE_FLR_WAIT_GUC: indicates that the PF awaits for a response from the GuC. 20 * @XE_GT_SRIOV_STATE_FLR_GUC_DONE: indicates that the PF has received a response from the GuC. 21 * @XE_GT_SRIOV_STATE_FLR_RESET_CONFIG: indicates that the PF needs to clear VF's resources. 22 * @XE_GT_SRIOV_STATE_FLR_RESET_DATA: indicates that the PF needs to clear VF's data. 23 * @XE_GT_SRIOV_STATE_FLR_RESET_MMIO: indicates that the PF needs to reset VF's registers. 24 * @XE_GT_SRIOV_STATE_FLR_SEND_FINISH: indicates that the PF wants to send a FLR FINISH message. 25 * @XE_GT_SRIOV_STATE_FLR_FAILED: indicates that VF FLR sequence failed. [all …]
/linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
H A D	other.json	9 …"PublicDescription": "This event counts every cycle that no operation was committed because the ol… 12 …"BriefDescription": "This event counts every cycle that no operation was committed because the old… 15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 33 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 36 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… [all …]
/linux/Documentation/process/
H A D	management-style.rst	14 to do with reality. It started as a lark, but that doesn't mean that it 27 making it painfully obvious to the questioner that we don't have a clue 37 Everybody thinks managers make decisions, and that decision-making is 39 manager must be to make it. That's very deep and obvious, but it's not 47 competent to make that decision for them. 51 Namely that you are in the wrong job, and that they should be managing 60 It helps to realize that the key difference between a big decision and a 62 can be made small by just always making sure that if you were wrong (and 67 And people will even see that as true leadership (cough bullshit 71 things that can't be undone. Don't get ushered into a corner from which [all …]
H A D	6.Followthrough.rst	8 patches. One of the biggest mistakes that even experienced kernel 9 developers can make is to conclude that their work is now done. In truth, 13 It is a rare patch which is so good at its first posting that there is no 16 code. You, as the author of that code, will be expected to work with the 17 kernel community to ensure that your code is up to the kernel's quality 32 value and why you went to the trouble of writing it. But that value 36 to substantial rewrites - come from the understanding that Linux will 49 be working on the kernel years from now, but they understand that their 57 the same. Sometimes this means that the clever hack in your driver 61 What all of this comes down to is that, when reviewers send you comments, [all …]
/linux/Documentation/filesystems/xfs/
H A D	xfs-delayed-logging-design.rst	10 This document describes the design and algorithms that the XFS journalling 11 subsystem is based on. This document describes the design and algorithms that 12 the XFS journalling subsystem is based on so that readers may familiarize 36 chained together by intents, ensuring that journal recovery can restart and 37 finish an operation that was only partially done when the system stopped 47 particularly important in the scope of this document. It suffices to know that 50 performed. The logging subsystem only cares that certain specific rules are 59 transactions. Permanent transaction reservations can take reservations that span 64 place. This means that permanent transactions can be used for one-shot 79 space that was taken at the transaction allocation time. [all …]
/linux/tools/memory-model/Documentation/
H A D	glossary.txt	9 dependency" extends from that load extending to the later access. 20 address dependency extends from that rcu_dereference() to that 27 Acquire: With respect to a lock, acquiring that lock, for example, 29 a special operation that includes a load and which orders that 30 load before later memory references running on that same CPU. 36 to that same variable, (in other words, the acquire load "reads 37 from" the release store), then all operations preceding that 38 store "happen before" any operations following that load acquire. 56 a "control dependency" extends from that load to that store. 71 that is required. In other cases, the notion of pairing must be [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/
H A D	tlb.json	4 …fills from any Instruction fetch. If there are multiple misses in the TLB that are resolved by the… 8 …on": "Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses … 12 …el 1 data TLB accesses caused by any memory load or store operation. Note that load or store instr… 28 …that partial translations that cause a translation table walk are also counted. Also note that thi… 32 …than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are als… 44 …ng a translation fault for reasons different than EPD, E0PD and NFD. Note that this event counts a… 52 …ng a translation fault for reasons different than EPD, E0PD and NFD. Note that this event counts a… 60 …that end up taking a translation fault are not counted, as the page size would be undefined in tha… 64 …that end up taking a translation fault are not counted, as the page size would be undefined in tha… 68 …that end up taking a translation fault are not counted, as the page size would be undefined in tha… [all …]
/linux/tools/perf/pmu-events/arch/x86/goldmont/
H A D	cache.json	7 …on which likely indicates back pressure from L2Q. It also counts requests that would have gone dir… 24 …"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That … 33 …"PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects… 41 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.", 50 …"PublicDescription": "Counts memory requests originating from the core that reference a cache line… 55 "BriefDescription": "Loads retired that came from DRAM (Precise event capable)", 72 …that when the load address was checked by other caching agents (typically another processor) in th… 77 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", 83 "PublicDescription": "Counts load uops retired that hit the L1 data cache.", 88 "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)", [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/
H A D	tlb.json	4 …fills from any Instruction fetch. If there are multiple misses in the TLB that are resolved by the… 8 …on": "Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses … 12 …el 1 data TLB accesses caused by any memory load or store operation. Note that load or store instr… 28 …that partial translations that cause a translation table walk are also counted. Also note that thi… 32 …than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are als… 36 …caused by memory read operations. If there are multiple misses in the TLB that are resolved by the… 40 …ata side memory write operations. If there are multiple misses in the TLB that are resolved by the… 92 …ng a translation fault for reasons different than EPD, E0PD and NFD. Note that this event counts a… 100 …ng a translation fault for reasons different than EPD, E0PD and NFD. Note that this event counts a… 108 …that end up taking a translation fault are not counted, as the page size would be undefined in tha… [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	uncore-cache.json	32 …"BriefDescription": "Counts transactions that looked into the multi-socket cacheline Directory sta… 42 …"BriefDescription": "Counts transactions that looked into the multi-socket cacheline Directory st… 168 …Note the non-standard filtering equation. This event will count requests that lookup the cache mu… 234 …Note the non-standard filtering equation. This event will count requests that lookup the cache mu… 256 …Note the non-standard filtering equation. This event will count requests that lookup the cache mu… 278 …Note the non-standard filtering equation. This event will count requests that lookup the cache mu… 289 …Note the non-standard filtering equation. This event will count requests that lookup the cache mu… 311 …Note the non-standard filtering equation. This event will count requests that lookup the cache mu… 344 …Note the non-standard filtering equation. This event will count requests that lookup the cache mu… 366 …Note the non-standard filtering equation. This event will count requests that lookup the cache mu… [all …]
/linux/LICENSES/preferred/
H A D	LGPL-2.1	45 price. Our General Public Licenses are designed to make sure that you have 47 service if you wish); that you receive source code or can get it if you 48 want it; that you can change the software and use pieces of it in new free 49 programs; and that you are informed that you can do these things. 51 To protect your rights, we need to make restrictions that forbid 57 a fee, you must give the recipients all the rights that we gave you. You 58 must make sure that they, too, receive or can get the source code. If you 60 the recipients, so that they can relink them with the library after making 68 To protect each distributor, we want to make it very clear that there is no 70 else and passed on, the recipients should know that what they have is not [all …]
H A D	LGPL-2.0	39 General Public Licenses are designed to make sure that you have the freedom 41 wish), that you receive source code or can get it if you want it, that you 42 can change the software or use pieces of it in new free programs; and that 45 To protect your rights, we need to make restrictions that forbid anyone to 51 a fee, you must give the recipients all the rights that we gave you. You 52 must make sure that they, too, receive or can get the source code. If you 54 the recipients so that they can relink them with the library, after making 62 Also, for each distributor's protection, we want to make certain that 63 everyone understands that there is no warranty for this free library. If 65 recipients to know that what they have is not the original version, so that [all …]
/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A D	memory.json	11 …"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for r… 21 …"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for d… 31 …"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for d… 41 …"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for r… 51 …"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for d… 61 …"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for d… 71 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 81 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 91 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 101 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… [all …]
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A D	uncore-cache.json	116 …Note the non-standard filtering equation. This event will count requests that lookup the cache mu… 182 …Note the non-standard filtering equation. This event will count requests that lookup the cache mu… 204 …Note the non-standard filtering equation. This event will count requests that lookup the cache mu… 226 …Note the non-standard filtering equation. This event will count requests that lookup the cache mu… 237 …Note the non-standard filtering equation. This event will count requests that lookup the cache mu… 259 …Note the non-standard filtering equation. This event will count requests that lookup the cache mu… 319 …escription": "Counts the number of lines that were victimized on a fill. This can be filtered by … 330 … IA traffic : Counts the number of lines that were victimized on a fill. This can be filtered by … 340 … IO traffic : Counts the number of lines that were victimized on a fill. This can be filtered by … 350 …escription": "Counts the number of lines that were victimized on a fill. This can be filtered by … [all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A D	core-imp-def.json	15 "PublicDescription": "Predictable branch speculatively executed that hit any level of BTB", 18 "BriefDescription": "Predictable branch speculatively executed that hit any level of BTB" 21 …"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of … 24 …"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of B… 27 …scription": "Predictable taken branch speculatively executed that hit any level of BTB that access… 30 …scription": "Predictable taken branch speculatively executed that hit any level of BTB that access… 33 …scription": "Predictable taken branch speculatively executed that hit any level of BTB that access… 36 …scription": "Predictable taken branch speculatively executed that hit any level of BTB that access… 39 …"PublicDescription": "Predictable unconditional branch speculatively executed that did not hit any… 42 …"BriefDescription": "Predictable unconditional branch speculatively executed that did not hit any … [all …]
/linux/Documentation/networking/devlink/
H A D	devlink-trap.rst	21 kernel so that it will route it as well and generate an ICMP Time Exceeded 39 as it allows users to obtain further visibility into packet drops that would 123 Generic packet traps are used to describe traps that trap well-defined packets 124 or packets that are trapped due to well-defined conditions (e.g., TTL error). 136 - Traps incoming packets that the device decided to drop because of a 140 - Traps incoming packets that the device decided to drop in case of VLAN 145 - Traps incoming packets that the device decided to drop in case they are 146 tagged with a VLAN that is not configured on the ingress bridge port 149 - Traps incoming packets that the device decided to drop in case the STP 153 - Traps packets that the device decided to drop in case they need to be [all …]

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