Searched +full:tegra186 +full:- +full:mc (Results 1 – 6 of 6) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.02 tegra-mc-y := mc.o4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o11 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o13 obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o[all …]
1 // SPDX-License-Identifier: GPL-2.0-only13 #include <dt-bindings/memory/tegra186-mc.h>17 #include <dt-bindings/memory/tegra194-mc.h>41 static void tegra186_mc_program_sid(struct tegra186_mc *mc) in tegra186_mc_program_sid() argument45 for (i = 0; i < mc->soc->num_clients; i++) { in tegra186_mc_program_sid()46 const struct tegra186_mc_client *client = &mc->soc->clients[i]; in tegra186_mc_program_sid()49 override = readl(mc->regs + client->regs.override); in tegra186_mc_program_sid()50 security = readl(mc->regs + client->regs.security); in tegra186_mc_program_sid()52 dev_dbg(mc->dev, "client %s: override: %x security: %x\n", in tegra186_mc_program_sid()53 client->name, override, security); in tegra186_mc_program_sid()[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra186 (and later) SoC Memory Controller10 - Jon Hunter <jonathanh@nvidia.com>11 - Thierry Reding <thierry.reding@gmail.com>14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split15 into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC16 handles memory requests for 40-bit virtual addresses from internal clients[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra186-clock.h>3 #include <dt-bindings/gpio/tegra186-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/memory/tegra186-mc.h>7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>8 #include <dt-bindings/power/tegra186-powergate.h>9 #include <dt-bindings/reset/tegra186-reset.h>10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra194-clock.h>3 #include <dt-bindings/gpio/tegra194-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>7 #include <dt-bindings/power/tegra194-powergate.h>8 #include <dt-bindings/reset/tegra194-reset.h>9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>10 #include <dt-bindings/memory/tegra194-mc.h>[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.8 #include <linux/clk-provider.h>17 #include <dt-bindings/clock/tegra210-car.h>18 #include <dt-bindings/reset/tegra210-car.h>23 #include "clk-id.h"264 * SDM fractional divisor is 16-bit 2's complement signed number within265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to275 #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \[all …]