| /linux-5.10/arch/arm64/boot/dts/nvidia/ |
| D | tegra186.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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| D | tegra234.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/reset/tegra234-reset.h>
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 compatible = "simple-bus";
16 #address-cells = <1>;
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| D | tegra194.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
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| D | tegra186-p3310.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra186.dtsi"
4 #include <dt-bindings/mfd/max77620.h>
8 compatible = "nvidia,p3310", "nvidia,tegra186";
12 i2c0 = "/bpmp/i2c";
27 stdout-path = "serial0:115200n8";
38 phy-reset-gpios = <&gpio TEGRA186_MAIN_GPIO(M, 4)
40 phy-handle = <&phy>;
41 phy-mode = "rgmii";
44 #address-cells = <1>;
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| /linux-5.10/Documentation/devicetree/bindings/firmware/ |
| D | nvidia,tegra186-bpmp.txt | 1 NVIDIA Tegra Boot and Power Management Processor (BPMP)
3 The BPMP is a specific processor in Tegra chip, which is designed for
6 defines the resources that would be used by the BPMP firmware driver,
8 and BPMP.
11 - compatible
14 - "nvidia,tegra186-bpmp"
15 - mboxes : The phandle of mailbox controller and the mailbox specifier.
16 - shmem : List of the phandle of the TX and RX shared memory area that
17 the IPC between CPU and BPMP is based on.
18 - #clock-cells : Should be 1.
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| /linux-5.10/Documentation/devicetree/bindings/thermal/ |
| D | nvidia,tegra186-bpmp-thermal.txt | 1 NVIDIA Tegra186 BPMP thermal sensor
3 In Tegra186, the BPMP (Boot and Power Management Processor) implements an
6 exposed by BPMP.
8 The BPMP thermal node must be located directly inside the main BPMP node. See
9 ../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
11 This node represents a thermal sensor. See Documentation/devicetree/bindings/thermal/thermal-sensor…
15 - compatible:
18 - "nvidia,tegra186-bpmp-thermal"
19 - "nvidia,tegra194-bpmp-thermal"
20 - #thermal-sensor-cells: Cell for sensor index.
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| /linux-5.10/Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra186-bpmp-i2c.txt | 1 NVIDIA Tegra186 BPMP I2C controller
3 In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
5 running on other CPUs must perform IPC to the BPMP in order to execute
9 The BPMP I2C node must be located directly inside the main BPMP node. See
10 ../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
16 - compatible:
19 - "nvidia,tegra186-bpmp-i2c".
20 - #address-cells: Address cells for I2C device address.
21 Single-cell integer.
23 - #size-cells:
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| /linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra186-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
16 handles memory requests for 40-bit virtual addresses from internal clients
27 pattern: "^memory-controller@[0-9a-f]+$"
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| /linux-5.10/drivers/firmware/tegra/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0-only
2 tegra-bpmp-y = bpmp.o
3 tegra-bpmp-$(CONFIG_ARCH_TEGRA_210_SOC) += bpmp-tegra210.o
4 tegra-bpmp-$(CONFIG_ARCH_TEGRA_186_SOC) += bpmp-tegra186.o
5 tegra-bpmp-$(CONFIG_ARCH_TEGRA_194_SOC) += bpmp-tegra186.o
6 tegra-bpmp-$(CONFIG_DEBUG_FS) += bpmp-debugfs.o
7 obj-$(CONFIG_TEGRA_BPMP) += tegra-bpmp.o
8 obj-$(CONFIG_TEGRA_IVC) += ivc.o
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| D | bpmp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <soc/tegra/bpmp.h>
19 #include <soc/tegra/bpmp-abi.h>
22 #include "bpmp-private.h"
37 struct tegra_bpmp *bpmp = channel->bpmp; in channel_to_ops() local
39 return bpmp->soc->ops; in channel_to_ops()
45 struct tegra_bpmp *bpmp; in tegra_bpmp_get() local
48 np = of_parse_phandle(dev->of_node, "nvidia,bpmp", 0); in tegra_bpmp_get()
50 return ERR_PTR(-ENOENT); in tegra_bpmp_get()
54 bpmp = ERR_PTR(-ENODEV); in tegra_bpmp_get()
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| /linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | nvidia,tegra186-dspk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra186-dspk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra186 DSPK Controller Device Tree Bindings
11 Density Modulation (PDM) transmitter that up-samples the input to
13 over sampled Pulse Code Modulation (PCM) input to the desired 1-bit
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^dspk@[0-9a-f]*$"
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| /linux-5.10/drivers/cpufreq/ |
| D | tegra186-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
12 #include <soc/tegra/bpmp.h>
13 #include <soc/tegra/bpmp-abi.h>
26 #define NO_CPU -1
61 for (i = 0; i < data->num_clusters; i++) { in tegra186_cpufreq_init()
62 struct tegra186_cpufreq_cluster *cluster = &data->clusters[i]; in tegra186_cpufreq_init()
64 cluster->info; in tegra186_cpufreq_init()
67 for (core = 0; core < ARRAY_SIZE(info->cpus); core++) { in tegra186_cpufreq_init()
68 if (info->cpus[core] == policy->cpu) in tegra186_cpufreq_init()
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| /linux-5.10/drivers/memory/tegra/ |
| D | tegra186-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <soc/tegra/bpmp.h>
20 struct tegra_bpmp *bpmp; member
38 * to control the EMC frequency. The top-level directory can be found here:
44 * - available_rates: This file contains a list of valid, space-separated
47 * - min_rate: Writing a value to this file sets the given frequency as the
52 * - max_rate: Similarily to the min_rate file, writing a value to this file
64 for (i = 0; i < emc->num_dvfs; i++) in tegra186_emc_validate_rate()
65 if (rate == emc->dvfs[i].rate) in tegra186_emc_validate_rate()
74 struct tegra186_emc *emc = s->private; in tegra186_emc_debug_available_rates_show()
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| /linux-5.10/drivers/thermal/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
9 Tegra systems-on-chip. The driver supports four thermal zones
15 tristate "Tegra BPMP thermal sensing"
19 Tegra systems-on-chip with the BPMP coprocessor (Tegra186).
|
| D | tegra-bpmp-thermal.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
16 #include <soc/tegra/bpmp.h>
17 #include <soc/tegra/bpmp-abi.h>
28 struct tegra_bpmp *bpmp; member
43 req.get_temp.zone = zone->idx; in tegra_bpmp_thermal_get_temp()
52 err = tegra_bpmp_transfer(zone->tegra->bpmp, &msg); in tegra_bpmp_thermal_get_temp()
69 req.set_trip.zone = zone->idx; in tegra_bpmp_thermal_set_trips()
79 return tegra_bpmp_transfer(zone->tegra->bpmp, &msg); in tegra_bpmp_thermal_set_trips()
89 thermal_zone_device_update(zone->tzd, THERMAL_TRIP_VIOLATED); in tz_device_update_work_fn()
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| /linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | nvidia,tegra20-pcie.txt | 4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
11 contain BPMP phandle and PCIe power partition ID. This is required only
12 for Tegra186.
13 - device_type: Must be "pci"
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| /linux-5.10/include/dt-bindings/thermal/ |
| D | tegra186-bpmp-thermal.h | 2 * This header provides constants for binding nvidia,tegra186-bpmp-thermal.
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| /linux-5.10/drivers/i2c/busses/ |
| D | i2c-tegra-bpmp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/i2c/busses/i2c-tegra-bpmp.c
19 #include <soc/tegra/bpmp-abi.h>
20 #include <soc/tegra/bpmp.h>
32 struct tegra_bpmp *bpmp; member
37 * Linux flags are translated to BPMP defined I2C flags that are used in BPMP
83 return (flags != 0) ? -EINVAL : 0; in tegra_bpmp_xlate_flags()
88 * [addr little-endian][flags little-endian][len little-endian][data if write]
89 * [addr little-endian][flags little-endian][len little-endian][data if write]
105 char *buf = request->xfer.data_buf; in tegra_bpmp_serialize_i2c_msg()
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| /linux-5.10/drivers/soc/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
63 # 64-bit ARM SoCs
75 Tegra124's "4+1" Cortex-A15 CPU complex.
85 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
88 and providing 256 CUDA cores. It supports hardware-accelerated en-
97 bool "NVIDIA Tegra186 SoC"
104 Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
105 combination of Denver and Cortex-A57 CPU cores and a GPU based on
106 the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
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| /linux-5.10/drivers/mailbox/ |
| D | tegra-hsp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
18 #include <dt-bindings/mailbox/tegra186-hsp.h>
111 return readl(hsp->regs + offset); in tegra_hsp_readl()
117 writel(value, hsp->regs + offset); in tegra_hsp_writel()
123 return readl(channel->regs + offset); in tegra_hsp_channel_readl()
129 writel(value, channel->regs + offset); in tegra_hsp_channel_writel()
136 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE); in tegra_hsp_doorbell_can_ring()
146 list_for_each_entry(entry, &hsp->doorbells, list) in __tegra_hsp_doorbell_get()
147 if (entry->master == master) in __tegra_hsp_doorbell_get()
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| /linux-5.10/drivers/gpu/drm/tegra/ |
| D | sor.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
504 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
506 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
510 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()
533 * Implementing ->set_parent() here isn't really required because the parent
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| /linux-5.10/drivers/clk/tegra/ |
| D | clk-tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/tegra210-car.h>
18 #include <dt-bindings/reset/tegra210-car.h>
23 #include "clk-id.h"
264 * SDM fractional divisor is 16-bit 2's complement signed number within
265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
275 #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \
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