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/linux-5.10/drivers/i2c/busses/
Di2c-sh_mobile.c219 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf) in sh_mobile_i2c_icch() argument
223 * ICCH >= COUNT_CLK * (tHIGH + tf) in sh_mobile_i2c_icch()
227 * the HIGH period of the SCL signal (tHIGH) after the SCL input in sh_mobile_i2c_icch()
230 * Afterward it turned out calculating ICCH using only tHIGH spec in sh_mobile_i2c_icch()
233 * condition, in order to meet both tHIGH and tHD;STA specs. in sh_mobile_i2c_icch()
235 return (((count_khz * (tHIGH + tf)) + 5000) / 10000); in sh_mobile_i2c_icch()
267 u32 tHIGH, tLOW, tf; in sh_mobile_i2c_init() local
273 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */ in sh_mobile_i2c_init()
277 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */ in sh_mobile_i2c_init()
286 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf); in sh_mobile_i2c_init()
Di2c-qcom-cci.c96 u16 thigh; /* HIGH period of the SCL clock in clock ticks */ member
276 val = hw->thigh << 16 | hw->tlow; in cci_init()
697 .thigh = 78,
709 .thigh = 20,
731 .thigh = 201,
743 .thigh = 38,
755 .thigh = 16,
Di2c-uniphier-f.c491 * Standard-mode: tLOW + tHIGH = 10 us in uniphier_fi2c_hw_init()
492 * Fast-mode: tLOW + tHIGH = 2.5 us in uniphier_fi2c_hw_init()
496 * Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us, tBUF = 4.7 us in uniphier_fi2c_hw_init()
497 * Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us, tBUF = 1.3 us in uniphier_fi2c_hw_init()
498 * "tLow/tHIGH = 5/4" meets both. in uniphier_fi2c_hw_init()
Di2c-uniphier.c301 * Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us in uniphier_i2c_hw_init()
302 * Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us in uniphier_i2c_hw_init()
303 * "tLow/tHIGH = 5/4" meets both. in uniphier_i2c_hw_init()
Di2c-designware-master.c63 4000, /* tHD;STA = tHIGH = 4.0 us */ in i2c_dw_set_timings_master()
93 260, /* tHIGH = 260 ns */ in i2c_dw_set_timings_master()
113 600, /* tHD;STA = tHIGH = 0.6 us */ in i2c_dw_set_timings_master()
140 160, /* tHIGH = 160 ns */ in i2c_dw_set_timings_master()
Di2c-designware-common.c335 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec in i2c_dw_scl_hcnt()
342 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH in i2c_dw_scl_hcnt()
359 * we could meet both tHIGH and tHD;STA timing specs. in i2c_dw_scl_hcnt()
Di2c-tegra.c593 u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; in tegra_i2c_init() local
626 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; in tegra_i2c_init()
637 thigh = i2c_dev->hw->thigh_std_mode; in tegra_i2c_init()
650 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) | in tegra_i2c_init()
662 clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); in tegra_i2c_init()
Di2c-mxs.c728 * tHIGH (SCL HIGH period) 4000 ns 600 ns in mxs_i2c_derive_timing()
Di2c-rk3x.c731 * tHigh = 8 * h * T;
Di2c-mlxbf.c336 u16 thigh_max; /* Thigh max. */
/linux-5.10/Documentation/devicetree/bindings/i2c/
Dsnps,designware-i2c.yaml86 This value is used to compute the tHIGH period.
/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dpptable_v1_0.h279 USHORT usPWMHigh; /* The PWM value at THigh. */
299 USHORT usPWMHigh; /* The PWM value at THigh. */
/linux-5.10/arch/powerpc/platforms/44x/
Dwarp.c196 i2c_smbus_write_byte_data(client, 2, 65); /* Thigh */ in pika_setup_critical_temp()
/linux-5.10/drivers/hwmon/
Dtmp108.c38 #define TMP108_CONF_FH 0x1000 /* Watchdog flag - THIGH */
/linux-5.10/drivers/gpu/drm/radeon/
Dpptable.h90 USHORT usPWMHigh; // The PWM value at THigh.
/linux-5.10/drivers/gpu/drm/amd/include/
Dpptable.h94 USHORT usPWMHigh; // The PWM value at THigh.
/linux-5.10/drivers/gpu/drm/amd/pm/inc/
Dhwmgr.h675 uint16_t usPWMHigh; /* The PWM value at THigh. */
/linux-5.10/tools/power/pm-graph/
Dsleepgraph.py4185 tHigh = ['', '']
4189 tHigh[i] = ' id="%smin" class=minval title="Minimum"' % tag
4191 tHigh[i] = ' id="%smax" class=maxval title="Maximum"' % tag
4193 tHigh[i] = ' id="%smed" class=medval title="Median"' % tag
4201 html += tdh.format('%.3f ms' % d[3], tHigh[0]) if d[3] else td.format('') # suspend
4202 html += tdh.format('%.3f ms' % d[4], tHigh[1]) if d[4] else td.format('') # resume