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/linux-6.8/Documentation/arch/riscv/
Dvm-layout.rst66 RISC-V Linux Kernel SV48
142 userspace from a 48-bit range (sv48). This default behavior is achieved by
144 smaller than sv48, the CPU maximum supported address space will be the default.
154 :code:`1 << 47` must be provided. Note that this is 47 due to sv48 userspace
/linux-6.8/Documentation/devicetree/bindings/riscv/
Dcpus.yaml74 - riscv,sv48
208 mmu-type = "riscv,sv48";
/linux-6.8/tools/testing/selftests/riscv/mm/
Dmmap_test.h27 * sv39, sv48, sv57 in do_mmaps()
/linux-6.8/arch/riscv/mm/
Dkasan_init.c15 * Kasan shadow region must lie at a fixed address across sv39, sv48 and sv57
21 * For sv48 and sv57, the region start is aligned on PGDIR_SIZE whereas the end
Dinit.c774 * meaning sv48 is supported.
/linux-6.8/Documentation/devicetree/bindings/cpu/
Didle-states.yaml785 mmu-type = "riscv,sv48";
801 mmu-type = "riscv,sv48";
817 mmu-type = "riscv,sv48";
833 mmu-type = "riscv,sv48";
/linux-6.8/Documentation/translations/zh_CN/arch/riscv/
Dvm-layout.rst71 RISC-V Linux Kernel SV48
/linux-6.8/arch/riscv/include/asm/
Dpage.h37 * define the PAGE_OFFSET value for SV48 and SV39.
Dpgtable.h858 * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu
/linux-6.8/arch/riscv/kernel/
Dcpu.c239 sv_type = "sv48"; in print_mmu()
/linux-6.8/tools/testing/selftests/kvm/lib/riscv/
Dprocessor.c189 * The RISC-V Sv48 MMU mode supports 56-bit physical address in riscv_vcpu_mmu_setup()