| /linux-5.10/arch/x86/include/asm/fpu/ |
| D | xstate.h | 37 /* All currently supported supervisor features */
41 * A supervisor state component may not always contain valuable information,
42 * and its size may be huge. Saving/restoring such supervisor state components
44 * be avoided. Such supervisor state components should only be saved/restored
45 * on demand. The on-demand dynamic supervisor features are set in this mask.
47 * Unlike the existing supported supervisor features, a dynamic supervisor
49 * supervisor state component cannot be saved/restored at each context switch.
51 * To support a dynamic supervisor feature, a developer should follow the
53 * - Do dynamically allocate a buffer for the supervisor state component.
56 * - Don't set the bit corresponding to the dynamic supervisor feature in
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| /linux-5.10/arch/m68k/ifpsp060/ |
| D | os.S | 58 | or supervisor application space. The examples below use simple "move"
59 | instructions for supervisor mode applications and call _copyin()/_copyout()
76 | Writes to data memory while in supervisor mode.
79 | a0 - supervisor source address
82 | 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
89 btst #0x5,0x4(%a6) | check for supervisor state
107 | Reads from data/instruction memory while in supervisor mode.
111 | a1 - supervisor destination address
113 | 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
122 btst #0x5,0x4(%a6) | check for supervisor state
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| D | CHANGES | 91 bit 18:16 = x10 (TM; x = 1 for supervisor mode)
113 bit 18:16 = x01 (TM; x = 1 for supervisor mode)
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| /linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
18 All RISC-V systems that conform to the supervisor ISA specification are
29 RISC-V supervisor ISA manual, with only the following three interrupts being
30 defined for supervisor mode:
31 - Source 1 is the supervisor software interrupt, which can be sent by an SBI
33 - Source 5 is the supervisor timer interrupt, which can be configured by
35 - Source 9 is the supervisor external interrupt, which chains to all other
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| /linux-5.10/arch/m68k/fpsp040/ |
| D | skeleton.S | 377 btst #0x5,%sp@ | supervisor bit set in saved SR?
387 | mem_write --- write to user or supervisor address space
389 | Writes to memory while in supervisor mode. copyout accomplishes
393 | a0 - supervisor source address
397 | The supervisor source address is guaranteed to point into the supervisor
404 | If the EXC_SR shows that the exception was from supervisor space,
406 | there shouldn't be any supervisor mode floating point exceptions.
410 btstb #5,EXC_SR(%a6) |check for supervisor state
427 | mem_read --- read from user or supervisor address space
429 | Reads from memory while in supervisor mode. copyin accomplishes
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| D | x_store.S | 167 exg %a0,%a1 |a0=supervisor source, a1=user dest
231 exg %a0,%a1 |a0=supervisor source, a1=user dest
251 exg %a0,%a1 |a0=supervisor source, a1=user dest
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| /linux-5.10/arch/x86/kernel/fpu/ |
| D | xstate.c | 60 * XSAVE buffer, both supervisor and user xstates.
118 * returns ECX[0] set to (1) for a supervisor state, and cleared (0) in xfeature_is_supervisor()
217 * Unsupported supervisor xstates should not be found in in fpu__init_cpu_xstate()
221 WARN_ONCE(unsup_bits, "x86/fpu: Found unsupported supervisor xstates: 0x%llx\n", in fpu__init_cpu_xstate()
236 * MSR_IA32_XSS sets supervisor states managed by XSAVES. in fpu__init_cpu_xstate()
281 * If an xfeature is supervisor state, the offset in EBX is in setup_xstate_features()
402 * Setup offsets of a supervisor-state-only XSAVES buffer:
480 * Only XSAVES supports supervisor states and it uses compacted in xfeature_uncompacted_offset()
481 * format. Checking a supervisor state's uncompacted offset is in xfeature_uncompacted_offset()
505 * 1. saving of supervisor/system state
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| D | signal.c | 237 * Supervisor state is unchanged by input from userspace. in sanitize_restored_user_xstate()
238 * Ensure supervisor state bits stay set and supervisor in sanitize_restored_user_xstate()
353 * Restore supervisor states: previous context switch in __fpu__restore_sig()
354 * etc has done XSAVES and saved the supervisor states in __fpu__restore_sig()
395 * Supervisor states are not modified by user space input. Save in __fpu__restore_sig()
396 * current supervisor states first and invalidate the FPU regs. in __fpu__restore_sig()
427 * Restore previously saved supervisor xstates along with in __fpu__restore_sig()
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| /linux-5.10/arch/powerpc/include/asm/book3s/32/ |
| D | mmu-hash.h | 57 #define PP_RWXX 0 /* Supervisor read/write, User none */
58 #define PP_RWRX 1 /* Supervisor read/write, User read */
59 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
60 #define PP_RXRX 3 /* Supervisor read, User read */
65 #define SR_KS 0x40000000 /* Supervisor key */
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| /linux-5.10/arch/microblaze/include/asm/ |
| D | mmu.h | 39 # define PP_RWXX 0 /* Supervisor read/write, User none */
40 # define PP_RWRX 1 /* Supervisor read/write, User read */
41 # define PP_RWRW 2 /* Supervisor read/write, User read/write */
42 # define PP_RXRX 3 /* Supervisor read, User read */
47 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
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| /linux-5.10/Documentation/hwmon/ |
| D | sl28cpld.rst | 21 supervisor. In the future there might be other flavours and additional
24 The fan supervisor has a 7 bit counter register and a counter period of 1
25 second. If the 7 bit counter overflows, the supervisor will automatically
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| /linux-5.10/arch/riscv/include/asm/ |
| D | csr.h | 13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
150 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
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| /linux-5.10/arch/m68k/include/asm/ |
| D | mcfdma.h | 89 #define MCFDMA_DMR_DSTT_SD 0x00001400L /* Destination is supervisor data */
90 #define MCFDMA_DMR_DSTT_SC 0x00001800L /* Destination is supervisor code */
101 #define MCFDMA_DMR_SRCT_SD 0x00000014L /* Source is supervisor data */
102 #define MCFDMA_DMR_SRCT_SC 0x00000018L /* Source is supervisor code */
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| D | m54xxacr.h | 36 #define ACR_SUPER 0x00002000 /* Supervisor mode only */
43 #define ACR_SP 0x00000008 /* Supervisor protect */
96 * cacheable and supervisor access only.
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| D | mcfmmu.h | 60 #define MMUSR_SPF 0x00000020 /* Supervisor protect fault */
79 #define MMUDR_SP 0x00000020 /* Supervisor access enable */
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| /linux-5.10/arch/sparc/include/asm/ |
| D | pcr.h | 20 #define PCR_STRACE 0x00000002 /* Trace supervisor events */
39 #define PCR_N4_STRACE 0x00000008 /* Trace supervisor events */
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| D | pgtsrmmu.h | 38 * for both supervisor and user pages.
42 * characteristics of supervisor ptes
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| D | iommu_32.h | 63 #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
77 #define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
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| /linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | nv50.c | 175 INIT_WORK(&disp->supervisor, func->super); in nv50_disp_new_()
311 HEAD_DBG(head, "supervisor 3.0"); in nv50_disp_super_3_0()
438 HEAD_DBG(head, "supervisor 2.2"); in nv50_disp_super_2_2()
482 HEAD_DBG(head, "supervisor 2.1 - %d khz", khz); in nv50_disp_super_2_1()
494 HEAD_DBG(head, "supervisor 2.0"); in nv50_disp_super_2_0()
517 HEAD_DBG(head, "supervisor 1.0"); in nv50_disp_super_1_0()
547 container_of(work, struct nv50_disp, supervisor); in nv50_disp_super()
553 nvkm_debug(subdev, "supervisor %08x %08x\n", disp->super, super); in nv50_disp_super()
678 queue_work(disp->wq, &disp->supervisor); in nv50_disp_intr()
751 /* enable supervisor interrupts, disable everything else */ in nv50_disp_init()
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| D | gf119.c | 37 container_of(work, struct nv50_disp, supervisor); in gf119_disp_super()
43 nvkm_debug(subdev, "supervisor %d\n", ffs(disp->super)); in gf119_disp_super()
151 queue_work(disp->wq, &disp->supervisor); in gf119_disp_intr()
235 /* enable supervisor interrupts, disable everything else */ in gf119_disp_init()
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| /linux-5.10/drivers/misc/eeprom/ |
| D | Kconfig | 62 tristate "Maxim MAX6874/5 power supply supervisor"
67 sequencer/supervisor.
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| /linux-5.10/arch/powerpc/include/asm/nohash/32/ |
| D | mmu-8xx.h | 33 * respectively NA for All or X for Supervisor and no access for User.
35 * "all Supervisor" rules (Access to all)
42 * 3 => User+Accessed => 00 (all accesses performed as supervisor iaw page definition) for INIT
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| D | pte-8xx.h | 46 #define _PAGE_NA 0x0200 /* Supervisor NA, User no access */
47 #define _PAGE_RO 0x0600 /* Supervisor RO, User no access */
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| /linux-5.10/arch/openrisc/include/asm/ |
| D | spr_defs.h | 215 #define SPR_SR_SM 0x00000001 /* Supervisor Mode */
231 #define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
275 #define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
276 #define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
517 #define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
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| /linux-5.10/Documentation/virt/kvm/ |
| D | hypercalls.rst | 82 shared page that contains parts of supervisor visible register state.
83 The guest can map this shared page to access its supervisor register
|