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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-int
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H A Driscv,imsics.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controlle
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H A Dthead,c900-aclint-sswi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controlle
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H A Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controlle
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/linux/tools/arch/riscv/include/asm/
H A Dcsr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
14 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
16 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
18 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
20 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
38 #define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Poin
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/linux/Documentation/arch/x86/x86_64/
H A Dfred.rst1 .. SPDX-License-Identifier: GPL-2.0
11 privilege level (ring transitions). The FRED architecture was
20 establishes the full supervisor context and that event return
33 The LKGS instruction can be used by 64-bit operating systems that do
46 framework must be implemented to facilitate the event-to-handler
48 once an event is delivered, and employs a two-level dispatc
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/linux/arch/microblaze/include/asm/
H A Dmmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
27 unsigned long w:1; /* Write-thru cache mode */
36 # define PP_RWXX 0 /* Supervisor read/write, User none */
37 # define PP_RWRX 1 /* Supervisor read/write, User read */
38 # define PP_RWRW 2 /* Supervisor read/write, User read/write */
39 # define PP_RXRX 3 /* Supervisor rea
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H A Dthread_info.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 * low level task data that entry.S needs immediate access to
22 * - this struct should fit entirely inside of one cache line
23 * - this struct shares the supervisor stack pages
24 * - if the contents of this structure are changed, the assembly constants
38 /* non-volatile registers */
61 unsigned long flags; /* low level flag
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/linux/arch/x86/kvm/
H A Dmmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
58 return ((2ULL << (e - s)) - 1) << s; in rsvd_bits()
76 return (1ULL << (max_gpa_bits - PAGE_SHIFT)) - 1; in kvm_mmu_max_gfn()
120 if (likely(vcpu->arch.mmu->root.hpa != INVALID_PAGE)) in kvm_mmu_reload()
150 u64 root_hpa = vcpu->arc in kvm_mmu_load_pgd()
268 gfn_to_index(gfn_t gfn,gfn_t base_gfn,int level) gfn_to_index() argument
277 __kvm_mmu_slot_lpages(struct kvm_memory_slot * slot,unsigned long npages,int level) __kvm_mmu_slot_lpages() argument
284 kvm_mmu_slot_lpages(struct kvm_memory_slot * slot,int level) kvm_mmu_slot_lpages() argument
289 kvm_update_page_stats(struct kvm * kvm,int level,int count) kvm_update_page_stats() argument
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/linux/arch/openrisc/include/asm/
H A Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
215 #define SPR_SR_SM 0x00000001 /* Supervisor Mode */
231 #define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
239 #define SPR_DMMUCR_P2S 0x0000003e /* Level
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H A Dthread_info.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
35 * low level task data that entry.S needs immediate access to
36 * - this struct should fit entirely inside of one cache line
37 * - this struct shares the supervisor stac
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/linux/tools/perf/pmu-events/arch/arm64/
H A Drecommended.json3 "PublicDescription": "Attributable Level 1 data cache access, read",
9 "PublicDescription": "Attributable Level 1 data cache access, write",
15 "PublicDescription": "Attributable Level 1 data cache refill, read",
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
27 "PublicDescription": "Attributable Level 1 data cache refill, inner",
33 "PublicDescription": "Attributable Level 1 data cache refill, outer",
39 "PublicDescription": "Attributable Level 1 data cache Write-Back, victim",
42 "BriefDescription": "L1D cache Write-Back, victim"
45 "PublicDescription": "Level
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/linux/arch/mips/include/asm/octeon/
H A Docteon.h6 * Copyright (C) 2004-2008 Cavium Networks
57 /* Start of block referenced by assembly code - do not change! */
66 /* End of This block referenced by assembly code - do not change! */
117 /* End of This block referenced by assembly code - do not change! */
124 * Warning low bit scrambled in little-endian.
182 /* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
189 /* OCTEON II - Selects the bit in the counter used for
196 /* OCTEON II - This field is an extension of
199 /* R/W If set, marked write-buffer entries time out
201 * write-buffe
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/linux/arch/powerpc/include/asm/nohash/32/
H A Dmmu-8xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * During software tablewalk, the registers used perform mask/shift-add
33 * respectively NA for All or X for Supervisor and no access for User.
35 * "all Supervisor" rules (Access to all)
43 * 4-15 => Not Used
57 /* A "level 1" or "segment" or whatever you want to call it register.
120 /* The pointer to the base address of the first level page table.
125 #define M_L1TB 0xfffff000 /* Level
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/linux/arch/nios2/include/asm/
H A Dthread_info.h2 * NiosII low-level thread information
30 * low level task data that entry.S needs immediate access to
31 * - this struct should fit entirely inside of one cache line
32 * - this struct shares the supervisor stack pages
33 * - if the contents of this structure are changed, the assembly constants
38 unsigned long flags; /* low level flags */
62 return (struct thread_info *)(sp & ~(THREAD_SIZE - 1)); in current_thread_info()
68 * - thes
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/linux/arch/arm/mach-imx/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0
42 * Set all MPROTx to be non-bufferable, trusted for R/W, in imx_set_aips()
43 * not forced to user-mode. in imx_set_aips()
49 * Set all OPACRx to be non-bufferable, to not require in imx_set_aips()
50 * supervisor privilege level for access, allow for in imx_set_aips()
/linux/arch/arc/include/asm/
H A Dthread_info.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
7 * anyways one page allocation, thus slab alloc can be short-circuited and
32 * low level task data that entry.S needs immediate access to
33 * - this struct should fit entirely inside of one cache line
34 * - thi
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/linux/arch/s390/include/asm/
H A Dthread_info.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 #define STACK_INIT_OFFSET (THREAD_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
30 * low level task data that entry.S needs immediate access to
31 * - this struct should fit entirely inside of one cache line
32 * - this struct shares the supervisor stack pages
33 * - i
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/linux/arch/nios2/mm/
H A Dfault.c7 * Copyright (C) 1995-2000 Ralf Baechle
32 #define EXC_SUPERV_INSN_ACCESS 9 /* Supervisor only instruction address */
33 #define EXC_SUPERV_DATA_ACCESS 11 /* Supervisor only data address */
48 struct mm_struct *mm = tsk->mm; in do_page_fault()
56 regs->ea -= 4; in do_page_fault()
59 * We fault-in kernel-space virtual memory on-demand. The in do_page_fault()
105 if (!(vma->vm_flag in do_page_fault()
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/linux/arch/xtensa/include/asm/
H A Dthread_info.h2 * include/asm-xtensa/thread_info.h
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
24 * low level task data that entry.S needs immediate access to
25 * - this struct should fit entirely inside of one cache line
26 * - this struct shares the supervisor stack pages
27 * - if the contents of this structure are changed, the assembly constants
50 unsigned long flags; /* low level flags */
51 unsigned long status; /* thread-synchronous flags */
65 * If i-t
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/linux/arch/x86/kvm/mmu/
H A Dpaging_tmpl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
19 * The MMU needs to be able to access/walk 32-bit and 64-bit guest page tables,
21 * once per guest PTE type. The per-type defines are #undef'd at the end.
50 (((1ULL << PT32_DIR_PSE36_SIZE) -
81 int level; global() member
202 unsigned level, index; FNAME() local
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/linux/Documentation/core-api/
H A Derrseq.rst13 It's implemented as an unsigned 32-bit value. The low order bits are
28 +---------
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/linux/arch/powerpc/include/asm/book3s/64/
H A Dmmu-hash.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 #include <asm/asm-const.h>
46 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
114 #define PP_RWXX 0 /* Supervisor read/write, User none */
115 #define PP_RWRX 1 /* Supervisor read/write, User read */
116 #define PP_RWRW 2 /* Supervisor rea
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-firmware-attributes1 What: /sys/class/firmware-attributes/*/attributes/*/
13 and will accept UTF-8 input.
21 - enumeration: a set of pre-defined valid values
22 - integer: a range of numerical values
23 - string
26 ----
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/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv1 # SPDX-License-Identifier: CC0-1.0
2 # Generator: x86-cpuid-db v2.4
5 # Auto-generated file.
6 # Please submit all updates and bugfixes to https://x86-cpuid.org
16 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
17 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
18 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 -
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