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/qemu/common-user/host/loongarch64/
H A Dsafe-syscall.inc.S2 * safe-syscall.inc.S : host-specific assembly fragment
4 * This is intended to be included by common-user/safe-syscall.S
8 * Based on safe-syscall.inc.S code for RISC-V,
13 * See the COPYING file in the top-level directory.
59 * stack frame; a6 is just the register we want here.
72 /* If signal_pending is non-zero, don't do the call */
78 li.w $t2, -4096
83 0: sub.d $a0, $zero, $a0
90 .size safe_syscall_base, .-safe_syscall_base
/qemu/target/hexagon/imported/
H A Dsubinsns.idef2 * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
19 * sub-instructions
26 /* A-type subinsns */
33 Q6INSN(SA1_setin1, "Rd16=#-1", ATTRIBS(A_SUBINSN),"Set to -1", { RdV=-1;})
41 Q6INSN(SA1_dec, "Rd16=add(Rs16,#-1)", ATTRIBS(A_SUBINSN),"Dec", { RdV=RsV-1;})
74 …e", ATTRIBS(A_REGWRSIZE_8B,A_SUBINSN,A_MEMSIZE_8B,A_LOAD,A_DEALLOCFRAME), "Deallocate stack frame",
82 …A_LOAD,A_RETURN,A_RESTRICT_SLOT0ONLY,A_RET_TYPE,A_DEALLOCRET), "Deallocate stack frame and return",
91 …A_MEMSIZE_8B,A_LOAD,A_RETURN,A_RESTRICT_SLOT0ONLY,A_RET_TYPE), "Deallocate stack frame and return",
95 …A_MEMSIZE_8B,A_LOAD,A_RETURN,A_RESTRICT_SLOT0ONLY,A_RET_TYPE), "Deallocate stack frame and return",
101 …A_MEMSIZE_8B,A_LOAD,A_RETURN,A_RESTRICT_SLOT0ONLY,A_RET_TYPE), "Deallocate stack frame and return",
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H A Dldst.idef2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
33 /* The set of 32-bit load instructions */
42 STD_LD_AMODES(loadbzw2, "Rd32=memubh", "Load Bytes and Vector Zero-Extend (unpack)",
51 STD_LD_AMODES(loadbzw4, "Rdd32=memubh", "Load Bytes and Vector Zero-Extend (unpack)",
63 STD_LD_AMODES(loadbsw2, "Rd32=membh", "Load Bytes and Vector Sign-Extend (unpack)",
72 STD_LD_AMODES(loadbsw4, "Rdd32=membh", "Load Bytes and Vector Sign-Extend (unpack)",
83 STD_LD_AMODES(loadalignh, "Ryy32=memh_fifo", "Load Half-word into shifted vector",
115 /* The set of 32-bit store instructions */
126 …3):raw", ATTRIBS(A_REGWRSIZE_8B,A_MEMSIZE_8B,A_STORE,A_RESTRICT_SLOT0ONLY), "Allocate stack frame",
127 …I(RxV,-8); fSTORE(1,8,EA,fFRAME_SCRAMBLE((fCAST8_8u(fREAD_LR()) << 32) | fCAST4_4u(fREAD_FP()))); …
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/qemu/target/arm/tcg/
H A Dm_helper.c6 * SPDX-License-Identifier: GPL-2.0-or-later
12 #include "cpu-features.h"
14 #include "exec/helper-proto.h"
15 #include "qemu/main-loop.h"
18 #include "exec/page-protection.h"
20 #include "accel/tcg/cpu-ldst.h"
21 #include "semihosting/common-semi.h"
63 uint32_t value = env->v7m.control[secure]; in arm_v7m_mrs_control()
67 value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; in arm_v7m_mrs_control()
80 case 0 ... 7: /* xPSR sub-fields */ in HELPER()
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/qemu/target/hexagon/
H A Dgenptr.c2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
21 #include "tcg/tcg-op.h"
22 #include "tcg/tcg-op-gvec.h"
23 #include "exec/helper-gen.h"
74 if (ctx->need_commit) { in get_result_gpr()
78 if (ctx->new_value[rnum] == NULL) { in get_result_gpr()
79 ctx->new_value[rnum] = tcg_temp_new(); in get_result_gpr()
80 tcg_gen_movi_tl(ctx->new_value[rnum], 0); in get_result_gpr()
82 return ctx->new_value[rnum]; in get_result_gpr()
120 if (ctx->need_commit) { in get_result_pred()
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H A Dattribs_def.h.inc2 * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
36 DEF_ATTRIB(SUBINSN, "sub-instruction", "", "")
53 DEF_ATTRIB(MEMLIKE, "Memory-like instruction", "", "")
54 DEF_ATTRIB(MEMLIKE_PACKET_RULES, "follows Memory-like packet rules", "", "")
87 /* Change-of-flow attributes */
88 DEF_ATTRIB(JUMP, "Jump-type instruction", "", "")
91 DEF_ATTRIB(COF, "Change-of-flow instruction", "", "")
92 DEF_ATTRIB(HINTED_COF, "This instruction is a hinted change-of-flow", "", "")
96 DEF_ATTRIB(NVSTORE, "New-value store", "", "")
99 DEF_ATTRIB(ROPS_2, "Compound instruction worth 2 RISC-ops", "", "")
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/qemu/include/hw/xen/interface/
H A Dxen.h1 /* SPDX-License-Identifier: MIT */
13 #include "xen-compat.h"
16 #include "arch-x86/xen.h"
18 #include "arch-arm.h"
118 /* Architecture-specific hypercall definitions. */
140 /* New event-channel and physdev hypercalls introduced in 0x00030202. */
158 * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a
159 * global VIRQ. The former can be bound once per VCPU and cannot be re-bound.
161 * allocated to VCPU0 but can subsequently be re-bound.
178 /* Architecture-specific VIRQ definitions. */
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/qemu/tests/qemu-iotests/
H A Diotests.py1 # Common utilities and Python wrappers for qemu-iotests
56 qemu_img_args = [os.environ.get('QEMU_IMG_PROG', 'qemu-img')]
60 qemu_io_args = [os.environ.get('QEMU_IO_PROG', 'qemu-io')]
64 qemu_io_args_no_fmt = [os.environ.get('QEMU_IO_PROG', 'qemu-io')]
69 qemu_nbd_prog = os.environ.get('QEMU_NBD_PROG', 'qemu-nbd')
77 qsd_prog = os.environ.get('QSD_PROG', 'qemu-storage-daemon')
105 valgrind_logfile = "--log-file=" + test_dir
111 qemu_valgrind = ['valgrind', valgrind_logfile, '--error-exitcode=99']
115 luks_default_key_secret_opt = 'key-secret=keysec0'
122 logger_name: str, level: int = logging.CRITICAL) -> Iterator[None]:
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/qemu/include/hw/xen/interface/io/
H A Dnetif.h1 /* SPDX-License-Identifier: MIT */
5 * Unified network-device I/O interface for Xen guest OSes.
7 * Copyright (c) 2003-2004, Keir Fraser
38 * feature 'feature-rx-notify' via xenbus. Otherwise the backend will assume
43 * "feature-split-event-channels" is introduced to separate guest TX
49 * "event-channel-tx" and "event-channel-rx" respectively. If frontend
50 * doesn't want to use this feature, it just writes "event-channel"
56 * If supported, the backend will write the key "multi-queue-max-queues" to
60 * key "multi-queue-num-queues", set to the number they wish to use, which
62 * in "multi-queue-max-queues".
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H A Dblkif.h1 /* SPDX-License-Identifier: MIT */
5 * Unified block-device I/O interface for Xen guest OSes.
7 * Copyright (c) 2003-2004, Keir Fraser
18 * Front->back notifications: When enqueuing a new request, sending a
20 * hold-off mechanism provided by the ring macros). Backends must set
23 * Back->front notifications: When enqueuing a new response, sending a
25 * hold-off mechanism provided by the ring macros). Frontends must set
63 *------------------ Backend Device Identification (PRIVATE) ------------------
78 * physical-device
85 * physical-device-path
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/qemu/dump/
H A Ddump.c10 * See the COPYING file in the top-level directory.
24 #include "qapi/qapi-commands-dump.h"
25 #include "qapi/qapi-events-dump.h"
27 #include "qemu/error-report.h"
28 #include "qemu/main-loop.h"
40 #include <snappy-c.h>
57 return s->dump_info.d_class == ELFCLASS64; in dump_is_64bit()
62 return s->filter_area_length > 0; in dump_has_filter()
67 if (s->dump_info.d_endian == ELFDATA2LSB) { in cpu_to_dump16()
78 if (s->dump_info.d_endian == ELFDATA2LSB) { in cpu_to_dump32()
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/qemu/tcg/i386/
H A Dtcg-target.c.inc94 /* The Win64 ABI has xmm6-xmm15 as caller-saves, and we do not save
95 any of them. Therefore only allow xmm0-xmm5 to be allocated. */
189 value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr);
198 value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr);
235 * TESTQ -> TESTL (uint32_t)
236 * TESTQ -> BT (is_power_of_2)
506 /* Group 1 opcode extensions for 0x80-0x83.
517 /* Group 2 opcode extensions for 0xc0, 0xc1, 0xd0-0xd3. */
540 #define JCC_JMP (-1)
582 /* We should never be asking for both 16 and 64-bit operation. */
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/qemu/include/standard-headers/linux/
H A Dethtool.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
19 #include "standard-headers/linux/const.h"
20 #include "standard-headers/linux/types.h"
21 #include "standard-headers/linux/if_ether.h"
26 * have the same layout for 32-bit and 64-bit userland.
38 * struct ethtool_cmd - DEPRECATED, link control and status
43 * interface supports autonegotiation or auto-detection.
44 * Read-only.
48 * auto-detection.
56 * @autoneg: Enable/disable autonegotiation and auto-detection;
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/qemu/pc-bios/
HDopenbios-sparc32 ... ) ['] display-ih cell+ ['] frame-buffer-adr cell+ ['] openbios-
HDopenbios-ppc ... i-cache-sets d-cache-block-size i-cache-block-size tlb- ...
/qemu/docs/specs/
H A Drocker.rst23 --------
30 -------------------------
39 * Register are (R) read-only, (R/W) read/write, (W) write-only, or (COR) clear
41 * TLV values in network-byte-order are designated with (N).
48 -----------------------
53 ---------------------------------------------
62 0xF 1 Built-in self test
65 0x18-28 Reserved
68 0x30-38 Reserved
77 * Assigned by sub-system implementation
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/qemu/tcg/mips/
H A Dtcg-target.c.inc4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
43 # define HI_OFF (4 - LO_OFF)
45 /* Assert at compile-time that these values are never used for 64-bit. */
160 /* Let the compiler perform the right-shift as part of the arithmetic. */
162 ptrdiff_t disp = target - (src_rx + 1);
187 #define TCG_CT_CONST_U16 0x100 /* Unsigned 16-bit: 0 - 0xffff. */
188 #define TCG_CT_CONST_S16 0x200 /* Signed 16-bit: -32768 - 32767 */
353 * backwards-compatible at the assembly level.
422 msb -= 32;
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/qemu/tcg/aarch64/
H A Dtcg-target.c.inc10 * See the COPYING file in the top-level directory for details.
28 /* We're going to re-use TCGType in setting of the SF bit, which controls
67 /* V8 - V15 are call-saved, and skipped. */
96 ptrdiff_t offset = target - src_rx;
110 ptrdiff_t offset = target - src_rx;
122 ptrdiff_t offset = target - src_rx;
159 /* Match a constant valid for addition (12-bit, optionally shifted). */
182 val += val & -val;
183 return (val & (val - 1)) == 0;
186 /* Return true if v16 is a valid 16-bit shifted immediate. */
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/qemu/include/standard-headers/drm/
H A Ddrm_fourcc.h38 * further describe the buffer's format - for example tiling or compression.
41 * ----------------
55 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * may preserve meaning - such as number of planes - from the fourcc code,
63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
75 * - Kernel and user-space drivers: for drivers it's important that modifiers
79 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
92 * -----------------------
97 * upstream in-kernel or open source userspace user does not apply.
221 * IEEE 754-2008 binary16 half-precision float
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/qemu/tcg/arm/
H A Dtcg-target.c.inc74 /* Q4 - Q7 are call-saved, and skipped. */
185 also Just So Happened to do nothing on pre-v6k so that we
273 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2;
285 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8;
287 if (offset >= -0xfff && offset <= 0xfff) {
291 offset = -offset;
304 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4;
306 if (offset >= -0xff && offset <= 0xff) {
310 offset = -offset;
323 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8;
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/qemu/
H A Dqemu-options.hx14 "-h or -help display this help and exit\n", QEMU_ARCH_ALL)
16 ``-h``
21 "-version display version information and exit\n", QEMU_ARCH_ALL)
23 ``-version``
28 "-machine [type=]name[,prop[=value][,...]]\n"
29 " selects emulated machine ('-machine help' for list)\n"
33 " dump-guest-core=on|off include guest memory in a core dump (default=on)\n"
34 " mem-merge=on|off controls memory merge support (default: on)\n"
35 " aes-key-wrap=on|off controls support for AES key wrapping (default=on)\n"
36 " dea-key-wrap=on|off controls support for DEA key wrapping (default=on)\n"
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/qemu/tcg/
H A Dtcg.c30 #include "qemu/error-report.h"
32 #include "qemu/host-utils.h"
33 #include "qemu/qemu-print.h"
38 #include "exec/translation-block.h"
39 #include "exec/tlb-common.h"
41 #include "tcg/tcg-op-common.h"
56 #include "tcg/tcg-ldst.h"
57 #include "tcg/tcg-temp-internal.h"
58 #include "tcg-internal.h"
60 #include "tcg-has.h"
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/qemu/hw/i386/
H A Dintel_iommu.c2 * QEMU emulation of an Intel IOMMU (VT-d)
23 #include "qemu/error-report.h"
24 #include "qemu/main-loop.h"
30 #include "hw/qdev-properties.h"
32 #include "hw/i386/apic-msidef.h"
33 #include "hw/i386/x86-iommu.h"
34 #include "hw/pci-host/q35.h"
45 ((ce)->val[1] & VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK)
47 ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK)
50 #define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT)
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