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/linux-5.10/Documentation/devicetree/bindings/crypto/
Dst,stm32-cryp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/st,stm32-cryp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lionel Debieve <lionel.debieve@st.com>
15 - st,stm32f756-cryp
16 - st,stm32mp1-cryp
27 resets:
31 - compatible
32 - reg
[all …]
Dst,stm32-hash.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/st,stm32-hash.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lionel Debieve <lionel.debieve@st.com>
15 - st,stm32f456-hash
16 - st,stm32f756-hash
27 resets:
33 dma-names:
35 - const: in
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/linux-5.10/Documentation/devicetree/bindings/clock/
Dst,stm32mp1-rcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gabriel Fernandez <gabriel.fernandez@st.com>
18 Documentation/devicetree/bindings/clock/clock-bindings.txt
24 dt-bindings/clock/stm32mp1-clks.h header and can be used in device
30 Device nodes should specify the reset channel required in their "resets"
38 For example on STM32MP1, for LTDC reset:
42 The list of valid indices for STM32MP1 is available in:
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/linux-5.10/Documentation/devicetree/bindings/mtd/
Dst,stm32-fmc2-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/st,stm32-fmc2-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@st.com>
15 - st,stm32mp15-fmc2
16 - st,stm32mp1-fmc2-nfc
27 - description: tx DMA channel
28 - description: rx DMA channel
29 - description: ecc DMA channel
[all …]
/linux-5.10/Documentation/devicetree/bindings/i2c/
Dst,stm32-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 - st,stm32f7-i2c
20 - st,stm32mp15-i2c
23 i2c-scl-rising-time-ns:
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/linux-5.10/Documentation/devicetree/bindings/remoteproc/
Dst,stm32-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/remoteproc/st,stm32-rproc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
14 - Fabien Dessenne <fabien.dessenne@st.com>
15 - Arnaud Pouliquen <arnaud.pouliquen@st.com>
19 const: st,stm32mp1-m4
27 resets:
30 st,syscfg-holdboot:
32 - Phandle of syscon block.
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/linux-5.10/arch/arm/boot/dts/
Dstm32mp151.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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Dstm32mp15xc.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
10 compatible = "st,stm32mp1-cryp";
14 resets = <&rcc CRYP1_R>;
/linux-5.10/Documentation/devicetree/bindings/media/
Dst,stm32-dcmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/st,stm32-dcmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hugues Fruchet <hugues.fruchet@st.com>
14 const: st,stm32-dcmi
25 clock-names:
27 - const: mclk
32 dma-names:
34 - const: tx
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/linux-5.10/Documentation/devicetree/bindings/display/
Dst,stm32-ltdc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-ltdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 lcd-tft display controller
10 - Philippe Cornu <philippe.cornu@st.com>
11 - Yannick Fertre <yannick.fertre@st.com>
15 const: st,stm32-ltdc
22 - description: events interrupt line.
23 - description: errors interrupt line.
[all …]
Dst,stm32-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Philippe Cornu <philippe.cornu@st.com>
11 - Yannick Fertre <yannick.fertre@st.com>
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
17 - $ref: dsi-controller.yaml#
21 const: st,stm32-dsi
28 - description: Module Clock
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/linux-5.10/Documentation/devicetree/bindings/spi/
Dst,stm32-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@st.com>
11 - Patrice Chotard <patrice.chotard@st.com>
14 - $ref: "spi-controller.yaml#"
18 const: st,stm32f469-qspi
22 - description: registers
23 - description: memory mapping
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Dst,stm32-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/st,stm32-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 the Serial Peripheral Interface. It supports full-duplex, half-duplex and
13 from 4 to 32-bit data size.
16 - Erwan Leray <erwan.leray@st.com>
17 - Fabrice Gasnier <fabrice.gasnier@st.com>
20 - $ref: "spi-controller.yaml#"
21 - if:
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/linux-5.10/Documentation/devicetree/bindings/dma/
Dst,stm32-dmamux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dmamux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Amelie Delaunay <amelie.delaunay@st.com>
13 - $ref: "dma-router.yaml#"
16 "#dma-cells":
20 const: st,stm32h7-dmamux
28 resets:
32 - compatible
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Dst,stm32-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
27 0x1: offset size is fixed to 4 (32-bit alignment)
[all …]
Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a five-cell specifier for each channel:
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
32 0x1: half-word (16bit)
[all …]
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dst,stm32-fmc2-ebi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@st.com>
26 const: st,stm32mp1-fmc2-ebi
34 resets:
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/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-stm32-usbphyc.txt14 |_ PHY port#2 ----| |________________
23 - compatible: must be "st,stm32mp1-usbphyc"
24 - reg: address and length of the usb phy control register set
25 - clocks: phandle + clock specifier for the PLL phy clock
26 - #address-cells: number of address cells for phys sub-nodes, must be <1>
27 - #size-cells: number of size cells for phys sub-nodes, must be <0>
30 - assigned-clocks: phandle + clock specifier for the PLL phy clock
31 - assigned-clock-parents: the PLL phy clock parent
32 - resets: phandle + reset specifier
34 Required nodes: one sub-node per port the controller provides.
[all …]
/linux-5.10/Documentation/devicetree/bindings/net/
Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/stm32-dwmac.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Alexandre Torgue <alexandre.torgue@st.com>
12 - Christophe Roullier <christophe.roullier@st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
26 - compatible
29 - $ref: "snps,dwmac.yaml#"
[all …]
/linux-5.10/Documentation/devicetree/bindings/timer/
Dst,stm32-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/st,stm32-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 general-purpose 16 and 32 bits timers bindings
10 - Benjamin Gaignard <benjamin.gaignard@st.com>
14 const: st,stm32-timer
25 resets:
29 - compatible
30 - reg
[all …]
/linux-5.10/Documentation/devicetree/bindings/rng/
Dst,stm32-rng.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rng/st,stm32-rng.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Lionel Debieve <lionel.debieve@st.com>
18 const: st,stm32-rng
26 resets:
29 clock-error-detect:
33 - compatible
34 - reg
[all …]
/linux-5.10/Documentation/devicetree/bindings/sound/
Dst,stm32-spdifrx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/st,stm32-spdifrx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Olivier Moysan <olivier.moysan@st.com>
14 IEC-60958 and IEC-61937.
19 - st,stm32h7-spdifrx
21 "#sound-dai-cells":
30 clock-names:
32 - const: kclk
[all …]
Dst,stm32-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/st,stm32-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Olivier Moysan <olivier.moysan@st.com>
19 - st,stm32h7-i2s
21 "#sound-dai-cells":
29 - description: clock feeding the peripheral bus interface.
30 - description: clock feeding the internal clock generator.
31 - description: I2S parent clock for sampling rates multiple of 8kHz.
[all …]
/linux-5.10/Documentation/devicetree/bindings/serial/
Dst,stm32-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Erwan Le Ray <erwan.leray@st.com>
13 - $ref: rs485.yaml
18 - st,stm32-uart
19 - st,stm32f7-uart
20 - st,stm32h7-uart
31 resets:
[all …]
/linux-5.10/Documentation/devicetree/bindings/iio/dac/
Dst,stm32-dac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/iio/dac/st,stm32-dac.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 The STM32 DAC is a 12-bit voltage output digital-to-analog converter. The DAC
11 may be configured in 8 or 12-bit mode. It has two output channels, each with
13 It has built-in noise and triangle waveform generator and supports external
18 - Fabrice Gasnier <fabrice.gasnier@st.com>
23 - st,stm32f4-dac-core
24 - st,stm32h7-dac-core
[all …]