Searched +full:stm32h7 +full:- +full:mdma (Results 1 – 5 of 5) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: STMicroelectronics STM32 MDMA Controller bindings10 The STM32 MDMA is a general-purpose direct memory access controller capable of12 DMA clients connected to the STM32 MDMA controller must use the format13 described in the dma.txt file, using a five-cell specifier for each channel:14 a phandle to the MDMA controller plus the following five integer cells:22 -bit 0-1: Source increment mode[all …]
2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>4 * This file is dual-licensed: you can use it either under the terms43 #include "armv7-m.dtsi"44 #include <dt-bindings/clock/stm32h7-clks.h>45 #include <dt-bindings/mfd/stm32h7-rcc.h>46 #include <dt-bindings/interrupt-controller/irq.h>49 #address-cells = <1>;50 #size-cells = <1>;53 clk_hse: clk-hse {54 #clock-cells = <0>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved6 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/clock/stm32mp1-clks.h>8 #include <dt-bindings/reset/stm32mp1-resets.h>11 #address-cells = <1>;12 #size-cells = <1>;15 #address-cells = <1>;16 #size-cells = <0>;19 compatible = "arm,cortex-a7";[all …]
1 // SPDX-License-Identifier: GPL-2.0-only6 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>8 * Driver for STM32 MDMA controller10 * Inspired by stm32-dma.c and dma-jz4780.c16 #include <linux/dma-mapping.h>33 #include "virt-dma.h"35 /* MDMA Generic getter/setter */36 #define STM32_MDMA_SHIFT(n) (ffs(n) - 1)42 #define STM32_MDMA_GISR0 0x0000 /* MDMA Int Status Reg 1 */43 #define STM32_MDMA_GISR1 0x0004 /* MDMA Int Status Reg 2 */[all …]
1 // SPDX-License-Identifier: GPL-2.08 #include <linux/clk-provider.h>18 #include <dt-bindings/clock/stm32h7-clks.h>139 /* Micro-controller output clock parent */178 bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy)); in ready_gate_clk_enable()183 } while (bit_status && --timeout); in ready_gate_clk_enable()201 bit_status = !!(readl(gate->reg) & BIT(rgate->bit_rdy)); in ready_gate_clk_disable()206 } while (bit_status && --timeout); in ready_gate_clk_disable()227 return ERR_PTR(-ENOMEM); in clk_register_ready_gate()235 rgate->bit_rdy = bit_rdy; in clk_register_ready_gate()[all …]