Searched +full:stm32 +full:- +full:rng (Results 1 – 14 of 14) sorted by relevance
/linux-6.15/Documentation/devicetree/bindings/rng/ |
D | st,stm32-rng.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/rng/st,stm32-rng.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: STMicroelectronics STM32 RNG 10 The STM32 hardware random number generator is a simple fixed purpose 14 - Lionel Debieve <lionel.debieve@foss.st.com> 19 - st,stm32-rng 20 - st,stm32mp13-rng 21 - st,stm32mp25-rng [all …]
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/linux-6.15/drivers/char/hw_random/ |
D | stm32-rng.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 7 #include <linux/clk-provider.h> 61 * struct stm32_rng_config - RNG configuration data 63 * @cr: RNG configuration. 0 means default hardware RNG configuration 74 struct hwrng rng; member 86 * Extracts from the STM32 RNG specification when RNG supports CONDRST. 88 * When a noise source (or seed) error occurs, the RNG stops generating 94 * Indeed, when SEIS is set and SECS is cleared it means RNG performed 95 * the reset automatically (auto-reset). 96 * 2. If SECS was set in step 1 (no auto-reset) wait for CONDRST [all …]
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D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 3 # Hardware Random Number Generator (RNG) configuration 13 module will be called rng-core. This provides a device 28 This driver provides kernel-side support for a generic Random 31 the default FPGA bitstream on the TS-7800 has such functionality. 34 module will be called timeriomem-rng. 43 This driver provides kernel-side support for the Random Number 44 Generator hardware found on Intel i8xx-based motherboards. 47 module will be called intel-rng. 57 This driver provides kernel-side support for the Random Number [all …]
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D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0 3 # Makefile for HW Random Number Generator (RNG) device drivers. 6 obj-$(CONFIG_HW_RANDOM) += rng-core.o 7 rng-core-y := core.o 8 obj-$(CONFIG_HW_RANDOM_TIMERIOMEM) += timeriomem-rng.o 9 obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o 10 obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o 11 obj-$(CONFIG_HW_RANDOM_AIROHA) += airoha-trng.o 12 obj-$(CONFIG_HW_RANDOM_ATMEL) += atmel-rng.o 13 obj-$(CONFIG_HW_RANDOM_BA431) += ba431-rng.o [all …]
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/linux-6.15/arch/arm/boot/dts/st/ |
D | stm32f429.dtsi | 2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 4 * This file is dual-licensed: you can use it either under the terms 22 * MA 02110-1301 USA 48 #include "../armv7-m.dtsi" 49 #include <dt-bindings/clock/stm32fx-clock.h> 50 #include <dt-bindings/mfd/stm32f4-rcc.h> 53 #address-cells = <1>; 54 #size-cells = <1>; 57 clk_hse: clk-hse { 58 #clock-cells = <0>; [all …]
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D | stm32mp131.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/clock/stm32mp13-clks.h> 8 #include <dt-bindings/reset/stm32mp13-resets.h> 11 #address-cells = <1>; 12 #size-cells = <1>; 15 #address-cells = <1>; 16 #size-cells = <0>; 19 compatible = "arm,cortex-a7"; [all …]
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D | stm32mp151.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/clock/stm32mp1-clks.h> 8 #include <dt-bindings/reset/stm32mp1-resets.h> 11 #address-cells = <1>; 12 #size-cells = <1>; 15 #address-cells = <1>; 16 #size-cells = <0>; 19 compatible = "arm,cortex-a7"; [all …]
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/linux-6.15/drivers/crypto/ |
D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0 2 obj-$(CONFIG_CRYPTO_DEV_ALLWINNER) += allwinner/ 3 obj-$(CONFIG_CRYPTO_DEV_ASPEED) += aspeed/ 4 obj-$(CONFIG_CRYPTO_DEV_ATMEL_AES) += atmel-aes.o 5 obj-$(CONFIG_CRYPTO_DEV_ATMEL_SHA) += atmel-sha.o 6 obj-$(CONFIG_CRYPTO_DEV_ATMEL_TDES) += atmel-tdes.o 7 # __init ordering requires atmel-i2c being before atmel-ecc and atmel-sha204a. 8 obj-$(CONFIG_CRYPTO_DEV_ATMEL_I2C) += atmel-i2c.o 9 obj-$(CONFIG_CRYPTO_DEV_ATMEL_ECC) += atmel-ecc.o 10 obj-$(CONFIG_CRYPTO_DEV_ATMEL_SHA204A) += atmel-sha204a.o [all …]
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D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 39 called padlock-aes. 53 called padlock-sha. 61 Say 'Y' here to use the AMD Geode LX processor on-board AES 65 will be called geode-aes. 87 - A pkey base and API kernel module (pkey.ko) which offers the 89 and the sysfs API and the in-kernel API to the crypto cipher 91 - A pkey pckmo kernel module (pkey-pckmo.ko) which is automatically 94 - A pkey CCA kernel module (pkey-cca.ko) which is automatically 96 - A pkey EP11 kernel module (pkey-ep11.ko) which is automatically [all …]
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/linux-6.15/drivers/platform/cznic/ |
D | turris-omnia-mcu.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 24 * struct omnia_mcu - driver private data structure 26 * @type: MCU type (STM32, GD32, MKL, or unknown) 49 * @rtcdev: RTC device, does not actually count real-time, the device is only 56 * @trng: RNG driver structure 57 * @trng_entropy_ready: RNG entropy ready completion
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/linux-6.15/arch/arm64/boot/dts/st/ |
D | stm32mp231.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved 6 #include <dt-bindings/clock/st,stm32mp25-rcc.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/regulator/st,stm32mp25-regulator.h> 9 #include <dt-bindings/reset/st,stm32mp25-rcc.h> 12 #address-cells = <2>; 13 #size-cells = <2>; 16 #address-cells = <1>; 17 #size-cells = <0>; [all …]
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D | stm32mp251.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 6 #include <dt-bindings/clock/st,stm32mp25-rcc.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/reset/st,stm32mp25-rcc.h> 9 #include <dt-bindings/regulator/st,stm32mp25-regulator.h> 10 #include <dt-bindings/phy/phy.h> 13 #address-cells = <2>; 14 #size-cells = <2>; 17 #address-cells = <1>; [all …]
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/linux-6.15/ |
D | MAINTAINERS | 5 --------------------------------------------------- 21 W: *Web-page* with status/info 23 B: URI for where to file *bugs*. A web-page with detailed bug 28 patches to the given subsystem. This is either an in-tree file, 29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst 46 N: [^a-z]tegra all files whose path contains tegra 64 ---------------- 83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS) 85 L: linux-scsi@vger.kernel.org 88 F: drivers/scsi/3w-* [all …]
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/linux-6.15/drivers/clk/stm32/ |
D | clk-stm32mp25.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 8 #include <linux/clk-provider.h> 12 #include "clk-stm32-core.h" 13 #include "reset-stm32.h" 16 #include <dt-bindings/clock/st,stm32mp25-rcc.h> 17 #include <dt-bindings/reset/st,stm32mp25-rcc.h> 20 #define SECF_NONE -1 523 /* CSI-HOST */ 539 /* CSI-PHY */ [all …]
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