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/linux/Documentation/devicetree/bindings/iio/pressure/
H A Dhoneywell,hsc030pa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Honeywell TruStability HSC and SSC pressure sensor series
10 support for Honeywell TruStability HSC and SSC digital pressure sensor
17 The vendor calls them "HSC series" and "SSC series". All of them have an
18 identical programming model but differ in pressure range, unit and transfer
21 To support different models one needs to specify the pressure range as well
22 as the transfer function. Pressure range can either be provided via
23 pressure-triplet (directly extracted from the part number) or in case it's
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/linux/Documentation/devicetree/bindings/phy/
H A Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
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H A Dst,stm32mp25-combophy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/st,stm32mp25-combophy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Bruel <christian.bruel@foss.st.com>
18 const: st,stm32mp25-combophy
23 "#phy-cells":
29 - description: apb Bus clock mandatory to access registers.
30 - description: ker Internal RCC reference clock for USB3 or PCIe
31 - description: pad Optional on board clock input for PCIe only. Typically an
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H A Dphy-miphy28lp.txt8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
12 Required nodes : A sub-node is required for each channel the controller
13 provides. Address range information including the usual
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
23 - PHY_TYPE_USB3
24 - reg : Address and length of the register set for the device.
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/linux/Documentation/devicetree/bindings/clock/
H A Dti,cdce925.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
13 Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction
15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
23 - ti,cdce913
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/linux/drivers/spi/
H A Dspi-st-ssc4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
25 /* SSC registers */
33 /* SSC Control */
48 /* SSC Interrupt Enable */
54 /* SSC SPI Controller */
59 /* SSC SPI current transaction */
74 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
77 count = spi_st->words_remaining; in ssc_write_tx_fifo()
80 if (spi_st->tx_ptr) { in ssc_write_tx_fifo()
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/linux/drivers/phy/st/
H A Dphy-miphy28lp.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <dt-bindings/phy/phy.h>
171 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
173 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
211 bool ssc; member
233 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
362 void __iomem *base = miphy_phy->base; in miphy28lp_set_reset()
373 /* Bringing the MIPHY-CPU registers out of reset */ in miphy28lp_set_reset()
374 if (miphy_phy->type == PHY_TYPE_PCIE) { in miphy28lp_set_reset()
386 void __iomem *base = miphy_phy->base; in miphy28lp_pll_calibration()
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/linux/sound/spi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 This driver requires the Atmel SSC driver for sound sink, a
25 called snd-at73c213.
31 range 8000 50000
/linux/block/
H A Dopal_proto.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * SPC-4 section
218 /* Locking state for a locking range */
283 * Opal SSC Documentation
337 * bits 6-7: reserved
369 * bits 1-6: reserved
380 * Enterprise SSC Feature
388 * bits 1-6: reserved
389 * bit 0: range crossing
419 * bits 3-7: reserved
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/linux/Documentation/ABI/testing/
H A Dsysfs-platform-dptf4 Contact: linux-acpi@vger.kernel.org
6 (RO) The charger type - Traditional, Hybrid or NVDC.
11 Contact: linux-acpi@vger.kernel.org
19 Contact: linux-acpi@vger.kernel.org
27 Contact: linux-acpi@vger.kernel.org
33 - 0x00 = DC
34 - 0x01 = AC
35 - 0x02 = USB
36 - 0x03 = Wireless Charger
43 Contact: linux-acpi@vger.kernel.org
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/linux/drivers/phy/renesas/
H A Dphy-rcar-gen3-usb3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car Gen3 for USB3.0 PHY driver
65 writew(val, r->base + USB30_CLKSET1); in write_clkset1_for_usb_extal()
72 switch (r->ssc_range) { in rcar_gen3_phy_usb3_enable_ssc()
83 dev_err(&r->phy->dev, "%s: unsupported range (%x)\n", __func__, in rcar_gen3_phy_usb3_enable_ssc()
84 r->ssc_range); in rcar_gen3_phy_usb3_enable_ssc()
88 writew(val, r->base + USB30_SSC_SET); in rcar_gen3_phy_usb3_enable_ssc()
94 if (r->ssc_range) in rcar_gen3_phy_usb3_select_usb_extal()
97 r->base + USB30_CLKSET0); in rcar_gen3_phy_usb3_select_usb_extal()
98 writew(PHY_ENABLE_RESET_EN, r->base + USB30_PHY_ENABLE); in rcar_gen3_phy_usb3_select_usb_extal()
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/linux/Documentation/scsi/
H A DFlashPoint.rst1 .. SPDX-License-Identifier: GPL-2.0
17 FREMONT, CA, -- October 8, 1996 -- Mylex Corporation has expanded Linux
33 Linux is a freely-distributed implementation of UNIX for Intel x86, Sun
35 machines. It supports a wide range of software, including the X Window
37 http://www.linux.org and http://www.ssc.com/.
55 and system boards. Through its wide range of RAID controllers and its
71 510/796-6100
78 BusLogic FlashPoint LT/BT-948 Upgrade Program
82 BusLogic FlashPoint LW/BT-958 Upgrade Program
99 customers to make sure the BT-946C/956C MultiMaster cards would still be
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/linux/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
109 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
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H A Dclk-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/tegra210-car.h>
18 #include <dt-bindings/reset/tegra210-car.h>
23 #include "clk-id.h"
264 * SDM fractional divisor is 16-bit 2's complement signed number within
265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
274 /* This macro returns ndiv effective scaled to SDM range */
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/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_10nm.c2 * SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <linux/clk-provider.h>
16 * DSI PLL 10nm - clock diagram (eg: DSI0):
21 * +---------+ | +----------+ | +----+
22 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
23 * +---------+ | +----------+ | +----+
27 * | | +----+ | |\ dsi0_pclk_mux
28 * | |--| /2 |--o--| \ |
29 * | | +----+ | \ | +---------+
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c1 // SPDX-License-Identifier: MIT
198 * the range value for them is (actual_value - 2).
310 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
311 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
315 * divided-down version of it.
320 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
321 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
323 clock->vco = clock->n == 0 ? 0 : in pnv_calc_dpll_params()
324 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
325 clock->dot = clock->p == 0 ? 0 : in pnv_calc_dpll_params()
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H A Dintel_dp_mst.c64 * DP MST (DisplayPort Multi-Stream Transport)
99 struct intel_digital_port *dig_port = intel_mst->primary; in to_primary_encoder()
101 return &dig_port->base; in to_primary_encoder()
108 struct intel_digital_port *dig_port = intel_mst->primary; in to_primary_dp()
110 return &dig_port->dp; in to_primary_dp()
115 return intel_dp->mst.active_streams; in intel_dp_mst_active_streams()
122 drm_dbg_kms(display->drm, "active MST streams %d -> %d\n", in intel_dp_mst_dec_active_streams()
123 intel_dp->mst.active_streams, intel_dp->mst.active_streams - 1); in intel_dp_mst_dec_active_streams()
125 if (drm_WARN_ON(display->drm, intel_dp->mst.active_streams == 0)) in intel_dp_mst_dec_active_streams()
128 return --intel_dp->mst.active_streams == 0; in intel_dp_mst_dec_active_streams()
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H A Dintel_display_regs.h1 /* SPDX-License-Identifier: MIT */
179 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
180 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)…
189 /* i830, required in DVO non-gang */
201 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
208 * digital display port. The range is 4 to 13; 10 or more
293 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
532 * Programmed value is multiplier - 1, up to 5x.
580 * of the infoframe structure specified by CEA-861. */
664 #define DP_PORT_WIDTH(width) REG_FIELD_PREP(DP_PORT_WIDTH_MASK, (width) - 1)
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/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
118 ret__ = -ETIMEDOUT; \
217 int pipe = gma_crtc->pipe; in cdv_dpll_set_clock_cdv()
272 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
288 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
290 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
293 } else if (clock->vco < 2750000) { in cdv_dpll_set_clock_cdv()
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/linux/drivers/clk/ti/
H A Ddpll3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
52 dd = clk->dpll_data; in _omap3_dpll_write_clken()
54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()
55 v &= ~dd->enable_mask; in _omap3_dpll_write_clken()
56 v |= clken_bits << __ffs(dd->enable_mask); in _omap3_dpll_write_clken()
57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in _omap3_dpll_write_clken()
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/linux/drivers/scsi/isci/
H A Dhost.c7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
100 * NORMALIZE_PUT_POINTER() -
110 * NORMALIZE_EVENT_POINTER() -
122 * NORMALIZE_GET_POINTER() -
131 * NORMALIZE_GET_POINTER_CYCLE_BIT() -
137 ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
140 * COMPLETION_QUEUE_CYCLE_BIT() -
152 sm->initial_state_id = initial_state; in sci_init_sm()
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/linux/drivers/i2c/busses/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 for Cypress CCGx Type-C controller. Individual bus drivers
25 controller is part of the 7101 device, which is an ACPI-compliant
29 will be called i2c-ali1535.
37 controller is part of the 7101 device, which is an ACPI-compliant
41 will be called i2c-ali1563.
51 will be called i2c-ali15x3.
63 will be called i2c-amd756.
73 will be called i2c-amd8111.
83 be called i2c-amd-mp2-pci and i2c-amd-mp2-plat.
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/linux/drivers/iio/pressure/
H A Dhsc030pa.c1 // SPDX-License-Identifier: GPL-2.0-only
7 …-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/bo…
36 * HSC_PRESSURE_TRIPLET_LEN - length for the string that defines the
37 * pressure range, measurement unit and type as per the part nomenclature.
38 * Consult honeywell,pressure-triplet in the bindings file for details.
51 * function A: 10% - 90% of 2^14
52 * function B: 5% - 95% of 2^14
53 * function C: 5% - 85% of 2^14
54 * function F: 4% - 94% of 2^14
140 * struct hsc_range_config - list of pressure ranges based on nomenclature
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c1 // SPDX-License-Identifier: MIT
79 clk_mgr->base.base.ctx->logger
118 for (i = 0; i < context->stream_count; i++) { in dcn314_get_active_display_cnt_wa()
119 const struct dc_stream_state *stream = context->streams[i]; in dcn314_get_active_display_cnt_wa()
121 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || in dcn314_get_active_display_cnt_wa()
122 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || in dcn314_get_active_display_cnt_wa()
123 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) in dcn314_get_active_display_cnt_wa()
127 if (dc_is_dp_signal(stream->signal) && !stream->dpms_off) in dcn314_get_active_display_cnt_wa()
132 for (i = 0; i < dc->link_count; i++) { in dcn314_get_active_display_cnt_wa()
133 const struct dc_link *link = dc->links[i]; in dcn314_get_active_display_cnt_wa()
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
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