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/linux-5.10/drivers/iio/gyro/
Dadxrs450.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/delay.h>
14 #include <linux/spi/spi.h>
25 /* The MSB for the spi commands */
67 * struct adxrs450_state - device instance specific data
68 * @us: actual spi_device
69 * @buf_lock: mutex to protect tx and rx
70 * @tx: transmit buffer
74 struct spi_device *us; member
76 __be32 tx ____cacheline_aligned;
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/linux-5.10/Documentation/devicetree/bindings/input/rmi4/
Drmi_spi.txt1 Synaptics RMI4 SPI Device Binding
5 bindings for devices using the SPI transport driver. Complete documentation
10 - compatible: syna,rmi4-spi
11 - reg: Chip select address for the device
12 - #address-cells: Set to 1 to indicate that the function child nodes
14 - #size-cells: Set to 0 to indicate that the function child nodes do not
18 - interrupts: interrupt which the rmi device is connected to.
19 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
21 - spi-rx-delay-us: microsecond delay after a read transfer.
22 - spi-tx-delay-us: microsecond delay after a write transfer.
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/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Controller Generic Binding
10 - Mark Brown <broonie@kernel.org>
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
20 pattern: "^spi(@.*|-[0-9a-f])*$"
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/linux-5.10/drivers/spi/
Dspi-dw-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
14 #include <linux/platform_data/dma-dw.h>
15 #include <linux/spi/spi.h>
18 #include "spi-dw.h"
29 if (s->dma_dev != chan->device->dev) in dw_spi_dma_chan_filter()
32 chan->private = s; in dw_spi_dma_chan_filter()
42 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
44 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
50 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
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Dspi-dw-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Designware SPI core controller driver (refer pxa2xx_spi.c)
8 #include <linux/dma-mapping.h>
13 #include <linux/delay.h>
15 #include <linux/spi/spi.h>
16 #include <linux/spi/spi-mem.h>
20 #include "spi-dw.h"
29 u32 rx_sample_dly; /* RX sample delay */
63 snprintf(name, 32, "dw_spi%d", dws->master->bus_num); in dw_spi_debugfs_init()
64 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
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Dspi-mpc512x-psc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC512x PSC in SPI mode driver.
7 * Hongjun Chen <hong-jun.chen@freescale.com>
22 #include <linux/delay.h>
24 #include <linux/spi/spi.h>
40 switch (mps->type) { \
42 struct mpc52xx_psc __iomem *psc = mps->psc; \
43 __ret = &psc->regname; \
47 struct mpc5125_psc __iomem *psc = mps->psc; \
48 __ret = &psc->regname; \
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Dspi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Addy Ke <addy.ke@rock-chips.com>
14 #include <linux/spi/spi.h>
18 #define DRIVER_NAME "rockchip-spi"
25 /* SPI register offsets */
67 /* ss_n to sclk_out delay */
150 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
154 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
173 const void *tx; member
195 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR); in spi_enable_chip()
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Dspi-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Broadcom BCM2835 SPI Controllers
10 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
11 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
32 #include <linux/spi/spi.h>
34 /* SPI register offsets */
75 #define DRV_NAME "spi-bcm2835"
81 "time in us to run a transfer in polling mode\n");
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Dspi-sifive.c1 // SPDX-License-Identifier: GPL-2.0
5 // SiFive SPI controller driver (master mode only)
15 #include <linux/spi/spi.h>
31 #define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
32 #define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
34 #define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
36 #define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
38 #define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
39 #define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
96 struct completion done; /* wake-up from interrupt */
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Dspi-bcm2835aux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Broadcom BCM2835 auxiliary SPI Controllers
8 * Based on: spi-bcm2835.c
16 #include <linux/delay.h>
28 #include <linux/spi/spi.h>
35 "time in us to run a transfer in polling mode - if zero no polling is used\n");
38 * spi register defines
47 /* SPI register offsets */
115 snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname); in bcm2835aux_debugfs_create()
119 bs->debugfs_dir = dir; in bcm2835aux_debugfs_create()
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Dspi-sprd.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/dma-mapping.h>
7 #include <linux/dma/sprd-dma.h>
18 #include <linux/spi/spi.h>
125 /* Default & maximum word delay cycles */
178 * SPI transmission time. in sprd_spi_transfer_max_timeout()
180 u32 size = t->bits_per_word * SPRD_SPI_FIFO_SIZE; in sprd_spi_transfer_max_timeout()
181 u32 bit_time_us = DIV_ROUND_UP(USEC_PER_SEC, ss->hw_speed_hz); in sprd_spi_transfer_max_timeout()
184 * There is an interval between data and the data in our SPI hardware, in sprd_spi_transfer_max_timeout()
187 u32 interval_cycle = SPRD_SPI_FIFO_SIZE * ss->word_delay; in sprd_spi_transfer_max_timeout()
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Dspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // SPI init/core code
11 #include <linux/dma-mapping.h>
16 #include <linux/clk/clk-conf.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi-mem.h>
29 #include <linux/delay.h>
38 #include <trace/events/spi.h>
48 struct spi_device *spi = to_spi_device(dev); in spidev_release() local
50 /* spi controllers may cleanup for released devices */ in spidev_release()
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/linux-5.10/net/nfc/nci/
Dspi.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/spi/spi.h>
12 #include <linux/crc-ccitt.h>
37 /* a NULL skb means we just want the SPI chip select line to raise */ in __nci_spi_send()
39 t.tx_buf = skb->data; in __nci_spi_send()
40 t.len = skb->len; in __nci_spi_send()
47 t.delay.value = nspi->xfer_udelay; in __nci_spi_send()
48 t.delay.unit = SPI_DELAY_UNIT_USECS; in __nci_spi_send()
49 t.speed_hz = nspi->xfer_speed_hz; in __nci_spi_send()
54 return spi_sync(nspi->spi, &m); in __nci_spi_send()
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/linux-5.10/Documentation/networking/
Dpktgen.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Enable CONFIG_NET_PKTGEN to compile and build pktgen either in-kernel
31 overload type of benchmarking, as this could hurt the normal use-case.
33 Specifically increasing the TX ring buffer in the NIC::
35 # ethtool -G ethX tx 1024
37 A larger TX ring can improve pktgen's performance, while it can hurt
38 in the general case, 1) because the TX ring buffer might get larger
43 TX ring cause delay. Drivers usually delay cleaning up the
44 ring-buffers for various performance reasons, and packets stalling
45 the TX ring might just be waiting for cleanup.
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/linux-5.10/arch/arm/boot/dts/
Dste-u300.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree for the ST-Ericsson U300 Machine and SoC
6 /dts-v1/;
9 model = "ST-Ericsson U300";
11 #address-cells = <1>;
12 #size-cells = <1>;
30 vana15-supply = <&ab3100_ldo_d_reg>;
35 compatible = "stericsson,u300-syscon", "syscon";
38 #clock-cells = <0>;
39 compatible = "fixed-clock";
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Dimx28-tx28.dts3 * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
5 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
45 #include <dt-bindings/gpio/gpio.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
49 model = "Ka-Ro electronics TX28 module";
70 reg = <0x40000000 0>; /* will be filled in by U-Boot */
74 compatible = "w1-gpio";
79 reg_usb0_vbus: regulator-usb0-vbus {
80 compatible = "regulator-fixed";
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/linux-5.10/arch/powerpc/boot/dts/
Dac14xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #address-cells = <1>;
15 #size-cells = <1>;
26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
49 compatible = "cfi-flash";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 bank-width = <2>;
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/linux-5.10/include/linux/iio/imu/
Dadis.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
12 #include <linux/spi/spi.h>
25 * struct adis_timeouts - ADIS chip variant timeouts
26 * @reset_ms - Wait time after rst pin goes inactive
27 * @sw_reset_ms - Wait time after sw reset command
28 * @self_test_ms - Wait time after self test command
36 * struct adis_data - ADIS chip variant specific data
37 * @read_delay: SPI delay for read operations in us
38 * @write_delay: SPI delay for write operations in us
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/linux-5.10/arch/arm64/boot/dts/qcom/
Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&intc>;
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Dqcs404.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
6 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/thermal/thermal.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
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/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h6-pine-h64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
6 #include "sun50i-h6.dtsi"
7 #include "sun50i-h6-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
13 compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
22 stdout-path = "serial0:115200n8";
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <32768>;
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/linux-5.10/drivers/input/rmi4/
Drmi_spi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2016 Synaptics Incorporated
11 #include <linux/spi/spi.h>
38 struct spi_device *spi; member
55 struct spi_device *spi = rmi_spi->spi; in rmi_spi_manage_pools() local
56 int buf_size = rmi_spi->xfer_buf_size in rmi_spi_manage_pools()
57 ? rmi_spi->xfer_buf_size : RMI_SPI_DEFAULT_XFER_BUF_SIZE; in rmi_spi_manage_pools()
68 tmp = rmi_spi->rx_buf; in rmi_spi_manage_pools()
69 buf = devm_kcalloc(&spi->dev, buf_size, 2, in rmi_spi_manage_pools()
72 return -ENOMEM; in rmi_spi_manage_pools()
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/linux-5.10/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
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/linux-5.10/Documentation/networking/dsa/
Dsja1105.rst10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
17 These are SPI-managed automotive switches, with all ports being gigabit
21 set-and-forget use, with minimal dynamic interaction at runtime. They
23 with CRC and table headers, and sent over SPI.
56 Also the configuration is write-only (software cannot read it back from the
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