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/linux-6.8/drivers/mtd/spi-nor/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 spi-nor-objs := core.o sfdp.o swp.o otp.o sysfs.o
4 spi-nor-objs += atmel.o
5 spi-nor-objs += eon.o
6 spi-nor-objs += esmt.o
7 spi-nor-objs += everspin.o
8 spi-nor-objs += gigadevice.o
9 spi-nor-objs += intel.o
10 spi-nor-objs += issi.o
11 spi-nor-objs += macronix.o
[all …]
Dsysfs.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/mtd/spi-nor.h>
4 #include <linux/spi/spi.h>
5 #include <linux/spi/spi-mem.h>
13 struct spi_device *spi = to_spi_device(dev); in manufacturer_show() local
14 struct spi_mem *spimem = spi_get_drvdata(spi); in manufacturer_show()
15 struct spi_nor *nor = spi_mem_get_drvdata(spimem); in manufacturer_show() local
17 return sysfs_emit(buf, "%s\n", nor->manufacturer->name); in manufacturer_show()
24 struct spi_device *spi = to_spi_device(dev); in partname_show() local
25 struct spi_mem *spimem = spi_get_drvdata(spi); in partname_show()
[all …]
Dcore.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* Standard SPI NOR flash operations. */
162 /* Dual SPI */
168 /* Quad SPI */
174 /* Octal SPI */
187 /* Quad SPI */
192 /* Octal SPI */
202 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
208 * @opcode: the SPI command op code to erase the sector/block.
223 * struct spi_nor_erase_command - Used for non-uniform erases
[all …]
Dcore.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mtd/spi-nor.h>
23 #include <linux/spi/flash.h>
30 * For everything but full-chip erase; probably could be much smaller, but kept
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
49 * @nor: pointer to a 'struct spi_nor'
57 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor, in spi_nor_get_cmd_ext() argument
60 switch (nor->cmd_ext_type) { in spi_nor_get_cmd_ext()
62 return ~op->cmd.opcode; in spi_nor_get_cmd_ext()
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SPI NOR device support"
8 This is the framework for the SPI NOR which can be used by the SPI
9 device drivers and the SPI NOR device driver.
34 This option disables the software write protection on any SPI
35 flashes at boot-up.
41 of your SPI flash. This is only to keep backwards compatibility.
46 Some SPI flashes have volatile block protection bits, ie. after a
47 power-up or a reset the flash is software write protected by
51 of flashes while keeping it enabled for any other SPI flashes
[all …]
Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/mtd/spi-nor.h>
5 #include <linux/spi/spi.h>
6 #include <linux/spi/spi-mem.h>
10 #define SPI_NOR_DEBUGFS_ROOT "spi-nor"
37 case SNOR_PROTO_1_1_1: return "1S-1S-1S"; in spi_nor_protocol_name()
38 case SNOR_PROTO_1_1_2: return "1S-1S-2S"; in spi_nor_protocol_name()
39 case SNOR_PROTO_1_1_4: return "1S-1S-4S"; in spi_nor_protocol_name()
40 case SNOR_PROTO_1_1_8: return "1S-1S-8S"; in spi_nor_protocol_name()
41 case SNOR_PROTO_1_2_2: return "1S-2S-2S"; in spi_nor_protocol_name()
[all …]
/linux-6.8/Documentation/devicetree/bindings/spi/
Dmediatek,spi-mtk-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Serial NOR flash controller for MediaTek ARM SoCs
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
14 This spi controller support single, dual, or quad mode transfer for
15 SPI NOR flash. There should be only one spi slave device following
16 generic spi bindings. It's not recommended to use this controller
[all …]
Dcdns,xspi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2020-21 Cadence
4 ---
5 $id: http://devicetree.org/schemas/spi/cdns,xspi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Parshuram Thombare <pthombar@cadence.com>
14 The XSPI controller allows SPI protocol communication in
16 read/write access to slaves such as SPI-NOR flash.
19 - $ref: spi-controller.yaml#
23 const: cdns,xspi-nor
[all …]
Daspeed,ast2600-fmc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
11 - Cédric Le Goater <clg@kaod.org>
15 SPI) of the AST2400, AST2500 and AST2600 SOCs.
18 - $ref: spi-controller.yaml#
23 - aspeed,ast2600-fmc
24 - aspeed,ast2600-spi
[all …]
/linux-6.8/Documentation/ABI/testing/
Dsysfs-bus-spi-devices-spi-nor1 What: /sys/bus/spi/devices/.../spi-nor/jedec_id
4 Contact: linux-mtd@lists.infradead.org
5 Description: (RO) The JEDEC ID of the SPI NOR flash as reported by the
10 non-JEDEC compliant flashes.
12 What: /sys/bus/spi/devices/.../spi-nor/manufacturer
15 Contact: linux-mtd@lists.infradead.org
16 Description: (RO) Manufacturer of the SPI NOR flash.
22 What: /sys/bus/spi/devices/.../spi-nor/partname
25 Contact: linux-mtd@lists.infradead.org
26 Description: (RO) Part name of the SPI NOR flash.
[all …]
/linux-6.8/include/linux/mtd/
Dspi-nor.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 #include <linux/spi/spi-mem.h>
18 * requires a 4-byte (32-bit) address.
30 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
31 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
32 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
33 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
34 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
35 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
53 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
[all …]
/linux-6.8/Documentation/devicetree/bindings/mtd/
Dhisilicon,fmc-spi-nor.txt1 HiSilicon SPI-NOR Flash Controller
4 - compatible : Should be "hisilicon,fmc-spi-nor" and one of the following strings:
5 "hisilicon,hi3519-spi-nor"
6 - address-cells : Should be 1.
7 - size-cells : Should be 0.
8 - reg : Offset and length of the register set for the controller device.
9 - reg-names : Must include the following two entries: "control", "memory".
10 - clocks : handle to spi-nor flash controller clock.
13 spi-nor-controller@10000000 {
14 compatible = "hisilicon,hi3519-spi-nor", "hisilicon,fmc-spi-nor";
[all …]
Djedec,spi-nor.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI NOR flash ST M25Pxx (and similar) serial flash chips
10 - Rob Herring <robh@kernel.org>
13 - $ref: mtd.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
19 - items:
20 - pattern: "^((((micron|spansion|st),)?\
[all …]
/linux-6.8/Documentation/driver-api/mtd/
Dspi-nor.rst2 SPI NOR framework
6 -----------------------------------
8 Most SPI NOR flashes comply with the JEDEC JESD216
11 standard set of internal read-only parameter tables.
13 The SPI NOR driver queries the SFDP tables in order to determine the
17 on its SFDP data. All one has to do is to specify the "jedec,spi-nor"
28 -----------------------------
31 section, after the ``---`` marker.
37 frequency using the Z (put compatible) SPI controller.
41 root@1:~# cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
[all …]
/linux-6.8/drivers/mtd/spi-nor/controllers/
Dnxp-spifi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI NOR driver for NXP SPI Flash Interface (SPIFI)
18 #include <linux/mtd/spi-nor.h>
21 #include <linux/spi/spi.h>
58 struct spi_nor nor; member
68 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_wait_for_cmd()
71 dev_warn(spifi->dev, "command timed out\n"); in nxp_spifi_wait_for_cmd()
81 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT); in nxp_spifi_reset()
82 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_reset()
85 dev_warn(spifi->dev, "state reset timed out\n"); in nxp_spifi_reset()
[all …]
Dhisi-sfc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * HiSilicon FMC SPI NOR flash controller driver
5 * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
9 #include <linux/dma-mapping.h>
13 #include <linux/mtd/spi-nor.h>
64 #define HIFMC_DMA_MASK (HIFMC_DMA_MAX_LEN - 1)
99 struct spi_nor *nor[HIFMC_MAX_CHIP_NUM]; member
107 return readl_poll_timeout(host->regbase + FMC_INT, reg, in hisi_spi_nor_wait_op_finish()
144 writel(reg, host->regbase + FMC_SPI_TIMING_CFG); in hisi_spi_nor_init()
147 static int hisi_spi_nor_prep(struct spi_nor *nor) in hisi_spi_nor_prep() argument
[all …]
/linux-6.8/arch/arm64/boot/dts/freescale/
Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
[all …]
Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
[all …]
Dfsl-ls1012a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "fsl-ls1012a.dtsi"
14 compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
21 sys_mclk: clock-mclk {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <24576000>;
27 reg_3p3v: regulator-3p3v {
28 compatible = "regulator-fixed";
[all …]
/linux-6.8/arch/powerpc/boot/dts/fsl/
Dmpc8536ds.dtsi2 * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
51 label = "diagnostic-nor";
[all …]
Dp1022ds.dtsi2 * P1022 DS Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
47 read-only;
[all …]
Dp1024rdb.dtsi2 * P1024 RDB Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
[all …]
Dp1020rdb-pd.dts2 * P1020 RDB-PD Device Tree Source (32-bit address map)
13 * * Neither the name of Freescale Semiconductor nor the
35 /include/ "p1020si-pre.dtsi"
37 model = "fsl,P1020RDB-PD";
38 compatible = "fsl,P1020RDB-PD";
47 /* NOR, NAND flash, L2 switch and CPLD */
53 nor@0,0 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 compatible = "cfi-flash";
[all …]
Dp1021rdb-pc.dtsi2 * P1021 RDB Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
[all …]
Dp2020rdb-pc.dtsi2 * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
[all …]

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