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/linux-5.10/drivers/spi/
Dspi-mux.c1 // SPDX-License-Identifier: GPL-2.0
3 // General Purpose SPI multiplexer
8 #include <linux/mux/consumer.h>
10 #include <linux/spi/spi.h>
12 #define SPI_MUX_NO_CS ((unsigned int)-1)
17 * This driver supports a MUX on an SPI bus. This can be useful when you need
21 * The driver will create an additional SPI controller. Devices added under the
22 * mux will be handled as 'chip selects' on this controller.
26 * struct spi_mux_priv - the basic spi_mux structure
27 * @spi: pointer to the device struct attached to the parent
[all …]
Dspi-dw-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
17 #include <linux/mux/consumer.h>
24 #include <linux/spi/spi-mem.h>
25 #include <linux/spi/spi.h>
27 #include "spi-dw.h"
35 struct mux_control *mux; member
52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()
54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()
55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()
[all …]
Dspi-meson-spicc.c2 * Driver for Amlogic Meson SPI communication controller (SPICC)
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
20 #include <linux/spi/spi.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
[all …]
/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-mux.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic SPI Multiplexer
10 This binding describes a SPI bus multiplexer to route the SPI chip select
11 signals. This can be used when you need more devices than the SPI controller
13 setting of the multiplexer to a channel needs to be done by a specific SPI mux
16 MOSI /--------------------------------+--------+--------+--------\
17 MISO |/------------------------------+|-------+|-------+|-------\|
[all …]
Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: "spi-controller.yaml#"
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
[all …]
Dspi-slave-mt27xx.txt1 Binding for MTK SPI Slave controller
4 - compatible: should be one of the following.
5 - mediatek,mt2712-spi-slave: for mt2712 platforms
6 - reg: Address and length of the register set for the device.
7 - interrupts: Should contain spi interrupt.
8 - clocks: phandles to input clocks.
10 - clock-names: should be "spi" for the clock gate.
13 - assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
14 - assigned-clock-parents: parent of mux clock.
16 - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.
[all …]
/linux-5.10/drivers/mux/
Dadgs1408.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ADGS1408/ADGS1409 SPI MUX driver
11 #include <linux/mux/driver.h>
13 #include <linux/spi/spi.h>
25 static int adgs1408_spi_reg_write(struct spi_device *spi, in adgs1408_spi_reg_write() argument
33 return spi_write_then_read(spi, tx_buf, sizeof(tx_buf), NULL, 0); in adgs1408_spi_reg_write()
36 static int adgs1408_set(struct mux_control *mux, int state) in adgs1408_set() argument
38 struct spi_device *spi = to_spi_device(mux->chip->dev.parent); in adgs1408_set() local
46 return adgs1408_spi_reg_write(spi, ADGS1408_SW_DATA, reg); in adgs1408_set()
53 static int adgs1408_probe(struct spi_device *spi) in adgs1408_probe() argument
[all …]
/linux-5.10/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
29 stdout-path = "serial0:115200n8";
37 sys_mclk: clock-mclk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <25000000>;
43 reg_1p8v: regulator-1p8v {
[all …]
/linux-5.10/arch/arm64/boot/dts/microchip/
Dsparx5_pcb125.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "microchip,sparx5-pcb125", "microchip,sparx5";
20 emmc_pins: emmc-pins {
28 drive-strength = <3>;
35 bus-width = <8>;
36 non-removable;
37 pinctrl-0 = <&emmc_pins>;
38 max-frequency = <8000000>;
39 microchip,clock-delay = <10>;
[all …]
Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
18 gpio-restart {
19 compatible = "gpio-restart";
26 i2cmux_pins_i: i2cmux-pins-i {
30 output-low;
32 i2cmux_s29: i2cmux-0 {
35 output-high;
37 i2cmux_s30: i2cmux-1 {
40 output-high;
[all …]
Dsparx5_pcb134_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
34 gpio-restart {
35 compatible = "gpio-restart";
43 spi@0 {
44 compatible = "spi-mux";
45 mux-controls = <&mux>;
46 #address-cells = <1>;
47 #size-cells = <0>;
49 spi-flash@9 {
[all …]
Dsparx5_nand.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 cs14_pins: cs14-pins {
14 pinctrl-0 = <&si2_pins>;
15 pinctrl-names = "default";
16 spi@e {
17 compatible = "spi-mux";
18 mux-controls = <&mux>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 spi-flash@6 {
[all …]
/linux-5.10/arch/arm/boot/dts/
Dmt7629-rfb.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
20 stdout-path = "serial0:115200n8";
23 gpio-keys {
24 compatible = "gpio-keys";
44 reg_3p3v: regulator-3p3v {
45 compatible = "regulator-fixed";
46 regulator-name = "fixed-3.3V";
[all …]
/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dlantiq,pinctrl-xway.txt4 - compatible: "lantiq,pinctrl-xway", (DEPRECATED: Use "lantiq,pinctrl-danube")
5 "lantiq,pinctrl-xr9", (DEPRECATED: Use "lantiq,xrx100-pinctrl" or
6 "lantiq,xrx200-pinctrl")
7 "lantiq,pinctrl-ase", (DEPRECATED: Use "lantiq,ase-pinctrl")
8 "lantiq,<chip>-pinctrl", where <chip> is:
14 - reg: Should contain the physical address and length of the gpio/pinmux
17 Please refer to pinctrl-bindings.txt in this directory for details of the
24 mux function to select on those group(s), and two pin configuration parameters:
25 pull-up and open-drain
31 other words, a subnode that lists a mux function but no pin configuration
[all …]
Dlantiq,pinctrl-falcon.txt4 - compatible: "lantiq,pinctrl-falcon"
5 - reg: Should contain the physical address and length of the gpio/pinmux
8 Please refer to pinctrl-bindings.txt in this directory for details of the
15 mux function to select on those group(s), and two pin configuration parameters:
16 pull-up and open-drain
22 other words, a subnode that lists a mux function but no pin configuration
25 information about e.g. the mux function.
29 Definition of mux function groups:
31 Required subnode-properties:
32 - lantiq,groups : An array of strings. Each string contains the name of a group.
[all …]
Dbrcm,bcm4708-pinmux.txt1 Broadcom Northstar pins mux controller
3 Some of Northstar SoCs's pins can be used for various purposes thanks to the mux
4 controller. This binding allows describing mux controller and listing available
14 - compatible: must be one of:
15 "brcm,bcm4708-pinmux"
16 "brcm,bcm4709-pinmux"
17 "brcm,bcm53012-pinmux"
18 - offset: offset of pin registers in the CRU block
21 - "spi": "spi_grp"
22 - "i2c": "i2c_grp"
[all …]
/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt7622-rfb1.dts6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
25 stdout-path = "serial0:115200n8";
31 proc-supply = <&mt6380_vcpu_reg>;
32 sram-supply = <&mt6380_vm_reg>;
36 proc-supply = <&mt6380_vcpu_reg>;
37 sram-supply = <&mt6380_vm_reg>;
[all …]
Dmt7622-bananapi-bpi-r64.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
16 model = "Bananapi BPI-R64";
17 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
24 stdout-path = "serial0:115200n8";
30 proc-supply = <&mt6380_vcpu_reg>;
31 sram-supply = <&mt6380_vm_reg>;
35 proc-supply = <&mt6380_vcpu_reg>;
[all …]
/linux-5.10/sound/soc/codecs/
Dwm8750.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8750.c -- WM8750 ALSA SoC audio driver
19 #include <linux/spi/spi.h>
145 SOC_ENUM("Playback De-emphasis", wm8750_enum[15]),
158 SOC_ENUM("Treble Cut-off", wm8750_enum[2]),
162 SOC_ENUM("3D Lower Cut-off", wm8750_enum[3]),
163 SOC_ENUM("3D Upper Cut-off", wm8750_enum[4]),
186 /* ADCDAC Bit 0 - ADCHPD */
187 /* ADCDAC Bit 4 - HPOR */
188 /* ADCTL1 Bit 2,3 - DATSEL */
[all …]
Dwm8988.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8988.c -- WM8988 ALSA SoC audio driver
17 #include <linux/spi/spi.h>
167 static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
168 static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
169 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
170 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
171 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
180 SOC_ENUM("Treble Cut-off", treble),
184 SOC_ENUM("3D Lower Cut-off", stereo_3d_lc),
[all …]
Dwm8770.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8770.c -- WM8770 ALSA SoC Audio driver
16 #include <linux/spi/spi.h>
105 regcache_mark_dirty(wm8770->regmap); \
114 static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0);
115 static const DECLARE_TLV_DB_SCALE(dac_dig_tlv, -12750, 50, 1);
116 static const DECLARE_TLV_DB_SCALE(dac_alg_tlv, -12700, 100, 1);
200 SOC_DAPM_ENUM("Capture Mux", ain_enum);
239 SND_SOC_DAPM_MUX("Capture Mux", WM8770_ADCMUX, 8, 1, &ain_mux),
269 { "Capture Mux", "AIN1", "AIN1" },
[all …]
/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-gx.dtsi"
7 #include "meson-gx-mali450.dtsi"
8 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
9 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
10 #include <dt-bindings/clock/gxbb-clkc.h>
11 #include <dt-bindings/clock/gxbb-aoclkc.h>
12 #include <dt-bindings/reset/gxbb-aoclkc.h>
15 compatible = "amlogic,meson-gxbb";
19 compatible = "amlogic,meson-gxbb-usb2-phy";
[all …]
/linux-5.10/Documentation/devicetree/bindings/soc/qcom/
Dqcom,gsbi.txt4 representing a serial sub-node device that is mux'd as part of the GSBI
9 - compatible: Should contain "qcom,gsbi-v1.0.0"
10 - cell-index: Should contain the GSBI index
11 - reg: Address range for GSBI registers
12 - clocks: required clock
13 - clock-names: must contain "iface" entry
14 - qcom,mode : indicates MUX value for configuration of the serial interface.
15 Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
18 - qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
19 dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
[all …]
/linux-5.10/drivers/clk/samsung/
Dclk-s3c2443.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/s3c2443.h>
18 #include "clk-pll.h"
71 MUX(0, "epllref", epllref_p, CLKSRC, 7, 2),
72 MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1),
73 MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1),
74 MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
75 MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1),
76 MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2),
[all …]
Dclk-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
17 #include "clk-pll.h"
98 /* S3C6400-specific parent clocks. */
103 /* S3C6410-specific parent clocks. */
126 MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1),
127 MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1),
128 MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1),
129 MUX(MOUT_MFC, "mout_mfc", mfc_p, CLK_SRC, 4, 1),
[all …]

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