Home
last modified time | relevance | path

Searched full:speedbin (Results 1 – 14 of 14) sorted by relevance

/linux-6.8/drivers/cpufreq/
Dqcom-cpufreq-nvmem.c11 * and speedbin blown in the efuse combination.
76 u8 *speedbin; in qcom_cpufreq_simple_get_version() local
79 speedbin = nvmem_cell_read(speedbin_nvmem, NULL); in qcom_cpufreq_simple_get_version()
80 if (IS_ERR(speedbin)) in qcom_cpufreq_simple_get_version()
81 return PTR_ERR(speedbin); in qcom_cpufreq_simple_get_version()
83 dev_dbg(cpu_dev, "speedbin: %d\n", *speedbin); in qcom_cpufreq_simple_get_version()
84 drv->versions = 1 << *speedbin; in qcom_cpufreq_simple_get_version()
85 kfree(speedbin); in qcom_cpufreq_simple_get_version()
174 u8 *speedbin; in qcom_cpufreq_kryo_name_version() local
182 speedbin = nvmem_cell_read(speedbin_nvmem, &len); in qcom_cpufreq_kryo_name_version()
[all …]
Dsun50i-cpufreq-nvmem.c39 u32 *speedbin, efuse_value; in sun50i_cpufreq_get_efuse() local
64 speedbin = nvmem_cell_read(speedbin_nvmem, &len); in sun50i_cpufreq_get_efuse()
66 if (IS_ERR(speedbin)) in sun50i_cpufreq_get_efuse()
67 return PTR_ERR(speedbin); in sun50i_cpufreq_get_efuse()
69 efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK; in sun50i_cpufreq_get_efuse()
81 kfree(speedbin); in sun50i_cpufreq_get_efuse()
/linux-6.8/Documentation/devicetree/bindings/opp/
Dopp-v2-kryo-cpu.yaml20 defines the voltage and frequency value based on the speedbin blown in
37 speedbin that is used to select the right frequency/voltage
58 0: MSM8996, speedbin 0
59 1: MSM8996, speedbin 1
60 2: MSM8996, speedbin 2
61 3: MSM8996, speedbin 3
64 Bitmap for MSM8996SG format (speedbin shifted of 4 left):
66 4: MSM8996SG, speedbin 0
67 5: MSM8996SG, speedbin 1
68 6: MSM8996SG, speedbin 2
[all …]
Dallwinner,sun50i-h6-operating-points.yaml17 on the speedbin blown in the efuse combination. The
31 registers that has information about the speedbin that is used
/linux-6.8/drivers/nvmem/
Dmtk-efuse.c54 * On some SoCs, the GPU speedbin is not read as bitmask but as in mtk_efuse_fixup_dt_cell_info()
59 strncmp(cell->name, "gpu-speedbin", min(sz, strlen("gpu-speedbin"))) == 0) in mtk_efuse_fixup_dt_cell_info()
/linux-6.8/drivers/gpu/drm/msm/adreno/
Dadreno_gpu.h84 uint16_t speedbin; member
106 * @speedbins: Optional table of fuse to speedbin mappings
117 * Helper to build a speedbin table, ie. the table:
118 * fuse | speedbin
138 uint16_t speedbin; member
497 int adreno_read_speedbin(struct device *dev, u32 *speedbin);
Dadreno_gpu.c335 *value |= ((uint64_t) adreno_gpu->speedbin) << 32; in adreno_get_param()
1060 int adreno_read_speedbin(struct device *dev, u32 *speedbin) in adreno_read_speedbin() argument
1062 return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); in adreno_read_speedbin()
1074 u32 speedbin; in adreno_gpu_init() local
1101 if (adreno_read_speedbin(dev, &speedbin) || !speedbin) in adreno_gpu_init()
1102 speedbin = 0xffff; in adreno_gpu_init()
1103 adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); in adreno_gpu_init()
Da6xx_gpu.c2717 return BIT(info->speedbins[i].speedbin); in fuse_to_supp_hw()
2725 u32 speedbin; in a6xx_set_supported_hw() local
2728 ret = adreno_read_speedbin(dev, &speedbin); in a6xx_set_supported_hw()
2730 * -ENOENT means that the platform doesn't support speedbin which is in a6xx_set_supported_hw()
2741 supp_hw = fuse_to_supp_hw(info, speedbin); in a6xx_set_supported_hw()
2746 speedbin); in a6xx_set_supported_hw()
Dadreno_device.c463 { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */
/linux-6.8/arch/arm/boot/dts/qcom/
Dqcom-ipq8064.dtsi380 speedbin_efuse: speedbin@c0 {
/linux-6.8/arch/arm64/boot/dts/qcom/
Dqcs404.dtsi376 cpr_efuse_speedbin: speedbin@13c {
Dmsm8996.dtsi769 speedbin_efuse: speedbin@133 {
Dsm8550.dtsi2022 /* Speedbin needs more work on A740+, keep only lower freqs */
/linux-6.8/arch/arm64/boot/dts/mediatek/
Dmt8186.dtsi1671 gpu_speedbin: gpu-speedbin@59c {