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/linux-6.8/Documentation/devicetree/bindings/clock/
Dqcom,sm4450-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM4450
10 - Ajit Pandey <quic_ajipan@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
15 domains on SM4450
17 See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h
21 const: qcom,sm4450-gcc
[all …]
Dqcom,rpmhcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <quic_tdas@quicinc.com>
20 - qcom,qdu1000-rpmh-clk
21 - qcom,sa8775p-rpmh-clk
22 - qcom,sc7180-rpmh-clk
23 - qcom,sc7280-rpmh-clk
24 - qcom,sc8180x-rpmh-clk
25 - qcom,sc8280xp-rpmh-clk
[all …]
/linux-6.8/arch/arm64/boot/dts/qcom/
Dsm4450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 interrupt-parent = <&intc>;
15 #address-cells = <2>;
16 #size-cells = <2>;
21 xo_board: xo-board {
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/linux-6.8/drivers/clk/qcom/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
[all …]
Dgcc-sm4450.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
20 #include "clk-regmap-phy-mux.h"
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
885 tristate "SM4450 Global Clock Controller"
889 Support for the global clock controller on SM4450 devices.
1145 tristate "High-Frequency PLL (HFPLL) Clock Controller"
1147 Support for the high-frequency PLLs present on Qualcomm devices.
1154 Support for the Krait ACC and GCC clock controllers. Say Y