Home
last modified time | relevance | path

Searched full:slcr (Results 1 – 8 of 8) sorted by relevance

/qemu/hw/arm/
H A Dxilinx_zynq.c81 * of the SLCR block. Clobbers r1.
208 DeviceState *dev, *slcr; in zynq_init() local
250 /* Create the main clock source, and feed slcr with it */ in zynq_init()
257 /* Create slcr, keep a pointer to connect clocks */ in zynq_init()
258 slcr = qdev_new("xilinx-zynq_slcr"); in zynq_init()
259 qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); in zynq_init()
260 qdev_prop_set_uint8(slcr, "boot-mode", zynq_machine->boot_mode); in zynq_init()
261 sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal); in zynq_init()
262 sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); in zynq_init()
296 qdev_get_clock_out(slcr, "uart0_ref_clk")); in zynq_init()
[all …]
H A Dxlnx-versal.c353 * - PMC SLCR in versal_create_pmc_apb_irq_orgate()
495 object_initialize_child(OBJECT(s), "versal-pmc-iou-slcr", &s->pmc.iou.slcr, in versal_create_pmc_iou_slcr()
498 sbd = SYS_BUS_DEVICE(&s->pmc.iou.slcr); in versal_create_pmc_iou_slcr()
577 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "ospi-mux-sel", 0, in versal_create_ospi()
874 "PMC SLCR parity interrupt behaviour " in versal_unimp_irq_parity_imr()
903 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 0, in versal_unimp()
907 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 1, in versal_unimp()
911 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), in versal_unimp()
916 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), in versal_unimp()
/qemu/include/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.h2 * Header file for the Xilinx Versal's PMC IOU SLCR
60 #define TYPE_XILINX_VERSAL_PMC_IOU_SLCR "xlnx.versal-pmc-iou-slcr"
/qemu/include/hw/arm/
H A Dxlnx-versal.h32 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
109 XlnxVersalPmcIouSlcr slcr; member
/qemu/docs/system/arm/
H A Dxlnx-zynq.rst18 - Zynq SLCR
/qemu/hw/misc/
H A Dmeson.build99 'xlnx-versal-pmc-iou-slcr.c',
H A Dzynq_slcr.c608 memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr", in zynq_slcr_init()
H A Dxlnx-versal-pmc-iou-slcr.c2 * QEMU model of Versal's PMC IOU SLCR (system level control registers)
34 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"