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/qemu/include/hw/i2c/
H A Di2c.h8 immediately. It does not support slave devices that need to be able to
9 defer their response (eg. CPU slave interfaces where the data is supplied
22 #define TYPE_I2C_SLAVE "i2c-slave"
29 /* Master to slave. Returns non-zero for a NAK, 0 for success. */
32 /* Master to slave (asynchronous). Receiving slave must call i2c_ack(). */
36 * Slave to master. This cannot fail, the device should always
42 * Notify the slave of a bus state change. For start event,
93 /* Set from slave currently mastering the bus. */
104 * @address: address of the slave
118 * @address: address of the slave
[all …]
H A Dbcm2835_i2c.h37 #define BCM2835_I2C_A 0xc /* Slave Address */
52 #define BCM2835_I2C_S_ERR BIT(8) /* Slave error */
H A Dsmbus_slave.h2 * QEMU SMBus device (slave) API
91 * SMBus slave data needs to be transferred.
H A Daspeed_i2c.h141 REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */
249 /* slave mode */
250 I2CSlave *slave; member
281 #define TYPE_ASPEED_I2C_BUS_SLAVE "aspeed.i2c.slave"
/qemu/include/hw/misc/
H A Dauxbus.h76 #define TYPE_AUX_SLAVE "aux-slave"
111 * @address The 20bits address of the slave.
128 * aux_init_mmio: Init an mmio for an AUX slave.
130 * @aux_slave The AUX slave.
135 /* aux_map_slave: Map the mmio for an AUX slave on the bus.
137 * @dev The AUX slave.
138 * @addr The address for the slave's mmio.
H A Dgrlib_ahb_apb_pnp.h35 uint8_t vendor, uint16_t device, int slave,
/qemu/hw/sd/
H A Dcore.c48 SDState *slave = get_card(sdbus); in sdbus_get_dat_lines() local
51 if (slave) { in sdbus_get_dat_lines()
52 SDCardClass *sc = SDMMC_COMMON_GET_CLASS(slave); in sdbus_get_dat_lines()
55 dat_lines = sc->get_dat_lines(slave); in sdbus_get_dat_lines()
65 SDState *slave = get_card(sdbus); in sdbus_get_cmd_line() local
68 if (slave) { in sdbus_get_cmd_line()
69 SDCardClass *sc = SDMMC_COMMON_GET_CLASS(slave); in sdbus_get_cmd_line()
72 cmd_line = sc->get_cmd_line(slave); in sdbus_get_cmd_line()
/qemu/docs/specs/
H A Dfsi.rst6 master/slave and the end engine.
27 2. The FSI slave: The slave is the terminal point of the FSI bus for FSI
29 slave's configuration registers appear in address space of the CFAM to
55 so complete; it's assumed that each CFAM is attached to a single FSI slave (as
56 a consequence the CFAM subclasses the FSI slave).
/qemu/hw/ppc/
H A Dpnv_chiptod.c11 * There is a master chip TOD, which sends signals to slave chip TODs to
50 #define TOD_S_PATH_CTRL_REG 0x00000005 /* Slave Path ctrl reg */
53 /* -- TOD primary/secondary master/slave control register -- */
56 /* -- TOD primary/secondary master/slave status register -- */
131 val |= PPC_BIT(25); /* Is slave (should backup master set this?) */ in pnv_chiptod_xscom_read()
243 "unimplemented slave register 0x%" PRIx32 "\n", reg); in chiptod_power9_tx_ttype_target()
268 "unimplemented slave register 0x%" PRIx32 "\n", reg); in chiptod_power10_tx_ttype_target()
320 " invalid slave address\n", val); in pnv_chiptod_xscom_write()
365 " TOD_MOVE_TOD_TO_TB_REG with no slave target\n"); in pnv_chiptod_xscom_write()
/qemu/hw/i2c/
H A Dimx_i2c.c119 "without specifying the slave address\n", in imx_i2c_read()
132 qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n", in imx_i2c_read()
179 } else { /* slave mode */ in imx_i2c_write()
230 /* If this is the first write cycle then it is the slave addr */ in imx_i2c_write()
253 qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n", in imx_i2c_write()
H A Dcore.c279 I2CSlave *slave = node->elt; in i2c_send_async() local
280 I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(slave); in i2c_send_async()
286 trace_i2c_send_async(slave->address, data); in i2c_send_async()
288 sc->send_async(slave, data); in i2c_send_async()
H A Daspeed_i2c.c59 "slave-match|" : "", in aspeed_i2c_bus_raise_interrupt()
512 /* No slave found */ in aspeed_i2c_bus_handle_cmd()
717 i2c_slave_set_address(bus->slave, bus->regs[R_I2CS_DEV_ADDR]); in aspeed_i2c_bus_new_write()
742 qemu_log_mask(LOG_UNIMP, "%s: Slave mode DMA TX is not implemented\n", in aspeed_i2c_bus_new_write()
780 "%s: Slave mode DMA TX Addr high is not implemented\n", in aspeed_i2c_bus_new_write()
812 i2c_slave_set_address(bus->slave, bus->regs[R_I2CD_DEV_ADDR]); in aspeed_i2c_bus_old_write()
1294 "%s: Slave mode RX DMA is not enabled\n", __func__); in aspeed_i2c_bus_new_slave_event()
1321 static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event) in aspeed_i2c_bus_slave_event() argument
1323 BusState *qbus = qdev_get_parent_bus(DEVICE(slave)); in aspeed_i2c_bus_slave_event()
1376 static void aspeed_i2c_bus_slave_send_async(I2CSlave *slave, uint8_t data) in aspeed_i2c_bus_slave_send_async() argument
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H A Dallwinner-i2c.c35 #define TWI_ADDR_REG 0x00 /* slave address register */
36 #define TWI_XADDR_REG 0x04 /* extended slave address register */
45 /* Used only in slave mode, do not set */
110 /* Slave mode */
/qemu/include/hw/display/
H A Di2c-ddc.h1 /* A simple I2C slave for returning monitor EDID data via DDC.
26 /* A simple I2C slave which just returns the contents of its EDID blob. */
/qemu/include/hw/nvram/
H A Deeprom_at24c.h15 * @address: I2C address of the EEPROM slave when put on a bus
27 * @address: I2C address of the EEPROM slave when put on a bus
/qemu/hw/fsi/
H A Dcfam.c123 FSISlaveState *slave = FSI_SLAVE(dev); in fsi_cfam_realize() local
125 /* Each slave has a 2MiB address space */ in fsi_cfam_realize()
136 memory_region_add_subregion(&cfam->mr, 0x800, &slave->iomem); in fsi_cfam_realize()
H A Dfsi.c84 dc->desc = "FSI Slave"; in fsi_slave_class_init()
/qemu/tests/functional/
H A Dtest_arm_aspeed_ast2600.py55 'echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-3/new_device',
56 'i2c i2c-3: new_device: Instantiated device slave-24c02 at 0x64')
60 'hexdump /sys/bus/i2c/devices/3-1064/slave-eeprom',
/qemu/docs/devel/
H A Dmulti-process.rst600 descriptor that QEMU can use for configuration, and a slave descriptor
602 would create both descriptors using the KVM driver, and pass the slave
720 *KVM\_DEV\_USER\_SLAVE\_FD* creates the slave file descriptor that will
721 be passed to the device emulation program. Only one slave can be created
726 address range that the slave descriptor will receive MMIO notifications
745 to destroy the slave descriptor; and free any memory allocated by the
748 slave descriptor
751 The slave descriptor will have its own file operations vector, which
775 There are several ioctl()s that can be performed on the slave
/qemu/include/hw/fsi/
H A Dfsi.h25 #define TYPE_FSI_SLAVE "fsi.slave"
/qemu/include/hw/ide/
H A Dide-bus.h11 IDEDevice *slave; member
/qemu/chardev/
H A Dchar-pty.c246 const char *slave; in openpty() local
260 if ((slave = ptsname(mfd)) == NULL) { in openpty()
264 if ((sfd = open(slave, O_RDONLY | O_NOCTTY)) == -1) { in openpty()
/qemu/tests/qtest/libqos/
H A Di2c-imx.c63 /* set the slave address */ in imx_i2c_send()
123 /* set the slave address */ in imx_i2c_recv()
/qemu/docs/system/
H A Dtarget-sparc.rst45 - Slave I/O: timers, interrupt controllers, Zilog serial ports,
/qemu/hw/ide/
H A Dide-dev.c62 if (bus->slave) { in ide_qdev_realize()
66 bus->slave = dev; in ide_qdev_realize()

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