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/linux-5.10/Documentation/devicetree/bindings/bus/
Dsimple-pm-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/bus/simple-pm-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple Power-Managed Bus
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 A Simple Power-Managed Bus is a transparent bus that doesn't need a real
16 However, its bus controller is part of a PM domain, or under the control
17 of a functional clock. Hence, the bus controller's PM domain and/or
18 clock must be enabled for child devices connected to the bus (either
[all …]
Drenesas,bsc.yaml2 ---
3 $id: http://devicetree.org/schemas/bus/renesas,bsc.yaml#
4 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 title: Renesas Bus State Controller (BSC)
9 - Geert Uytterhoeven <geert+renesas@glider.be>
12 The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
13 Bridge", or "External Bus Interface") can be found in several Renesas ARM
14 SoCs. It provides an external bus for connecting multiple external
18 While the BSC is a fairly simple memory-mapped bus, it may be part of a
24 The bindings for the BSC extend the bindings for "simple-pm-bus".
[all …]
Dmvebu-mbus.txt6 - compatible: Should be set to one of the following:
7 marvell,armada370-mbus
8 marvell,armadaxp-mbus
9 marvell,armada375-mbus
10 marvell,armada380-mbus
11 marvell,kirkwood-mbus
12 marvell,dove-mbus
13 marvell,orion5x-88f5281-mbus
14 marvell,orion5x-88f5182-mbus
15 marvell,orion5x-88f5181-mbus
[all …]
/linux-5.10/Documentation/devicetree/bindings/arm/
Darm,realview.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
22 - description: ARM RealView Emulation Baseboard (HBI-0140) was created
26 - const: arm,realview-eb
27 - description: ARM RealView Platform Baseboard for ARM1176JZF-S
28 (HBI-0147) was created as a development board to test ARM TrustZone,
31 - const: arm,realview-pb1176
[all …]
Darm,vexpress-juno.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
37 further subvariants are released of the core tile, even more fine-granular
45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
49 - const: arm,vexpress,v2p-ca9
[all …]
/linux-5.10/arch/arm/boot/dts/
Dimx6q-gw54xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
8 #include "imx6qdl-gw54xx.dtsi"
9 #include <dt-bindings/media/tda1997x.h>
13 compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
15 sound-digital {
16 compatible = "simple-audio-card";
17 simple-audio-card,name = "tda1997x-audio";
18 simple-audio-card,format = "i2s";
19 simple-audio-card,bitclock-master = <&sound_codec>;
[all …]
Datlas6.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 d-cache-line-size = <32>;
21 i-cache-line-size = <32>;
22 d-cache-size = <32768>;
23 i-cache-size = <32768>;
[all …]
Dprima2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 d-cache-line-size = <32>;
23 i-cache-line-size = <32>;
24 d-cache-size = <32768>;
[all …]
Ddra7-evm-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
6 #include "dra74-ipu-dsp-common.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/ti-dra7-atl.h>
9 #include <dt-bindings/input/input.h>
13 stdout-path = &uart1;
17 compatible = "linux,extcon-usb-gpio";
18 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
22 compatible = "linux,extcon-usb-gpio";
[all …]
Drda8810pl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&intc>;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a5";
29 compatible = "mmio-sram";
31 #address-cells = <1>;
[all …]
Dvf610-twr.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 /dts-v1/;
10 compatible = "fsl,vf610-twr", "fsl,vf610";
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <24576000>;
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <50000000>;
34 compatible = "simple-bus";
[all …]
Dls1021a-twr.dts2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
5 * This file is dual-licensed: you can use it either under the terms
23 * MA 02110-1301 USA
49 /dts-v1/;
54 compatible = "fsl,ls1021a-twr", "fsl,ls1021a";
62 sys_mclk: clock-mclk {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <24576000>;
69 compatible = "simple-bus";
[all …]
/linux-5.10/drivers/bus/
Dsimple-pm-bus.c2 * Simple Power-Managed Bus Driver
4 * Copyright (C) 2014-2015 Glider bvba
19 struct device_node *np = pdev->dev.of_node; in simple_pm_bus_probe()
21 dev_dbg(&pdev->dev, "%s\n", __func__); in simple_pm_bus_probe()
23 pm_runtime_enable(&pdev->dev); in simple_pm_bus_probe()
26 of_platform_populate(np, NULL, NULL, &pdev->dev); in simple_pm_bus_probe()
33 dev_dbg(&pdev->dev, "%s\n", __func__); in simple_pm_bus_remove()
35 pm_runtime_disable(&pdev->dev); in simple_pm_bus_remove()
40 { .compatible = "simple-pm-bus", },
49 .name = "simple-pm-bus",
[all …]
/linux-5.10/Documentation/devicetree/bindings/mfd/
Dmfd.txt1 Multi-Function Devices (MFD)
4 more than one non-unique yet varying hardware functionality.
8 - A mixed signal ASIC on an external bus, sometimes a PMIC (Power Management
14 - A range of memory registers containing "miscellaneous system registers" also
20 - compatible : "simple-mfd" - this signifies that the operating system should
22 "simple-bus" indicates when to see subnodes as children for a simple
23 memory-mapped bus. For more complex devices, when the nexus driver has to
28 - ranges: Describes the address mapping relationship to the parent. Should set
32 - #address-cells: Specifies the number of cells used to represent physical base
35 - #size-cells: Specifies the number of cells used to represent the size of an
[all …]
Daspeed-lpc.txt2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
6 peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
7 primary use case of the Aspeed LPC controller is as a slave on the bus
9 conditions it can also take the role of bus master.
11 The LPC controller is represented as a multi-function device to account for the
24 APB-to-LPC bridging amonst other functions.
27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
28 management and bus snoop configuration.
39 [1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c888374547021…
[all …]
/linux-5.10/Documentation/devicetree/bindings/soc/imx/
Dfsl,aips-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,aips-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
14 AHB bus and peripherals with the lower bandwidth IP Slave (IPS)
21 const: fsl,aips-bus
23 - compatible
28 - const: fsl,aips-bus
29 - const: simple-bus
[all …]
/linux-5.10/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
29 stdout-path = "serial0:115200n8";
37 sys_mclk: clock-mclk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <25000000>;
43 reg_1p8v: regulator-1p8v {
[all …]
Dfsl-ls1012a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "fsl-ls1012a.dtsi"
14 compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
16 sys_mclk: clock-mclk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <24576000>;
22 reg_3p3v: regulator-3p3v {
23 compatible = "regulator-fixed";
[all …]
Dfsl-ls1012a-frdm.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "fsl-ls1012a.dtsi"
14 compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
16 sys_mclk: clock-mclk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <25000000>;
22 reg_1p8v: regulator-1p8v {
23 compatible = "regulator-fixed";
[all …]
/linux-5.10/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,brcmstb.txt2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
23 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
[all …]
/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-gx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/power/meson-gxbb-power.h>
16 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
17 #include <dt-bindings/thermal/thermal.h>
20 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <2>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/net/
Dmarvell,prestera.txt2 -------------------------------------
5 - compatible: must be "marvell,prestera" and one of the following
6 "marvell,prestera-98dx3236",
7 "marvell,prestera-98dx3336",
8 "marvell,prestera-98dx4251",
9 - reg: address and length of the register set for the device.
10 - interrupts: interrupt for the device
13 - dfx: phandle reference to the "DFX Server" node
18 compatible = "simple-bus";
19 #address-cells = <1>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/c6x/
Demifa.txt2 -------------------------
4 The emifa node describes a simple external bus controller found on some C6X
9 - compatible: must be "ti,c64x+emifa", "simple-bus"
10 - reg: register area base and size
11 - #address-cells: must be 2 (chip-select + offset)
12 - #size-cells: must be 1
13 - ranges: mapping from EMIFA space to parent space
18 - ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR
20 - ti,emifa-burst-priority:
26 - ti,emifa-ce-config:
[all …]
/linux-5.10/arch/arm64/boot/dts/realtek/
Drtd129x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2016-2019 Andreas Färber
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/realtek,rtd1295.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
Drtd139x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/realtek,rtd1295.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
34 no-map;
[all …]

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