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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-sifive.yaml4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
7 title: SiFive SPI controller
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
21 - sifive,fu540-c000-spi
22 - sifive,fu740-c000-spi
23 - const: sifive,spi0
26 Should be "sifive,<chip>-spi" and "sifive,spi<version>".
28 "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
[all …]
/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-sifive.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
8 title: SiFive PWM controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 Unlike most other PWM controllers, the SiFive PWM controller currently
21 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
30 - sifive,fu540-c000-pwm
31 - sifive,fu740-c000-pwm
32 - const: sifive,pwm0
34 Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dsifive,fu540-c000-pdma.yaml4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
7 title: SiFive Unleashed Rev C000 Platform DMA
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 Platform DMA is a DMA engine of SiFive Unleashed. It supports 4
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
34 - const: sifive,pdma0
38 - sifive,fu540-c000-pdma
39 - const: sifive,pdma0
[all …]
/linux/Documentation/devicetree/bindings/serial/
H A Dsifive-serial.yaml4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
21 - sifive,fu540-c000-uart
22 - sifive,fu740-c000-uart
24 - const: sifive,uart0
27 Should be something similar to "sifive,<chip>-uart"
29 and "sifive,uart<version>" for the general UART IP
[all …]
/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi2 /* Copyright (c) 2018-2019 SiFive, Inc */
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
11 compatible = "sifive,fu540-c000", "sifive,fu540";
26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
44 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
71 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
98 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
125 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
182 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
196 compatible = "sifive,fu540-c000-prci";
[all …]
H A Dfu740-c000.dtsi2 /* Copyright (c) 2020 SiFive, Inc */
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
11 compatible = "sifive,fu740-c000", "sifive,fu740";
26 compatible = "sifive,bullet0", "riscv";
45 compatible = "sifive,bullet0", "riscv";
72 compatible = "sifive,bullet0", "riscv";
99 compatible = "sifive,bullet0", "riscv";
126 compatible = "sifive,bullet0", "riscv";
185 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
197 compatible = "sifive,fu740-c000-prci";
[all …]
H A Dhifive-unleashed-a00.dts2 /* Copyright (c) 2018-2019 SiFive, Inc */
13 model = "SiFive HiFive Unleashed A00";
14 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
15 "sifive,fu540";
/linux/Documentation/devicetree/bindings/sifive/
H A Dsifive-blocks-ip-versioning.txt1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
23 "sifive,uart0" to indicate that their driver is compatible with the
25 upstream sifive-blocks commits. It is expected that most drivers will
30 "sifive,fu540-c000-uart". This way, if SoC-specific
33 IP block-specific compatible string (such as "sifive,uart0") should
[all …]
/linux/Documentation/devicetree/bindings/cache/
H A Dsifive,ccache0.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
8 title: SiFive Composable Cache Controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 The SiFive Composable Cache Controller is used to provide access to fast copies
24 - sifive,ccache0
25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
36 - sifive,ccache0
37 - sifive,fu540-c000-ccache
[all …]
/linux/Documentation/devicetree/bindings/riscv/
H A Dsifive.yaml4 $id: http://devicetree.org/schemas/riscv/sifive.yaml#
7 title: SiFive SoC-based boards
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 SiFive SoC-based boards
23 - sifive,hifive-unleashed-a00
24 - const: sifive,fu540-c000
25 - const: sifive,fu540
29 - sifive,hifive-unmatched-a00
30 - const: sifive,fu740-c000
[all …]
H A Dcpus.yaml10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
51 - sifive,bullet0
52 - sifive,e5
53 - sifive,e7
54 - sifive,e71
55 - sifive,rocket0
56 - sifive,s7
57 - sifive,u5
58 - sifive,u54
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dsifive,gpio.yaml4 $id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#
7 title: SiFive GPIO controller
10 - Paul Walmsley <paul.walmsley@sifive.com>
16 - sifive,fu540-c000-gpio
17 - sifive,fu740-c000-gpio
19 - const: sifive,gpio0
44 It is 16 for the SiFive SoCs and 32 for the Canaan K210.
69 - sifive,fu540-c000-gpio
70 - sifive,fu740-c000-gpio
79 #include <dt-bindings/clock/sifive-fu540-prci.h>
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
39 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
41 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
43 The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
48 - Paul Walmsley <paul.walmsley@sifive.com>
62 - sifive,fu540-c000-plic
66 - const: sifive,plic-1.0.0
[all …]
/linux/Documentation/devicetree/bindings/clock/sifive/
H A Dfu740-prci.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/clock/sifive/fu740-prci.yaml#
8 title: SiFive FU740 Power Reset Clock Interrupt Controller (PRCI)
11 - Zong Li <zong.li@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
18 macros defined in include/dt-bindings/clock/sifive-fu740-prci.h.
27 const: sifive,fu740-c000-prci
59 compatible = "sifive,fu740-c000-prci";
H A Dfu540-prci.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11 - Paul Walmsley <paul.walmsley@sifive.com>
17 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
26 const: sifive,fu540-c000-prci
55 compatible = "sifive,fu540-c000-prci";
/linux/Documentation/devicetree/bindings/pci/
H A Dsifive,fu740-pcie.yaml4 $id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
7 title: SiFive FU740 PCIe host controller
10 SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
16 - Paul Walmsley <paul.walmsley@sifive.com>
17 - Greentime Hu <greentime.hu@sifive.com>
24 const: sifive,fu740-pcie
84 #include <dt-bindings/clock/sifive-fu740-prci.h>
90 compatible = "sifive,fu740-pcie";
/linux/drivers/edac/
H A Dsifive_edac.c3 * SiFive Platform EDAC Driver
5 * Copyright (C) 2018-2022 SiFive, Inc.
13 #include <soc/sifive/sifive_ccache.h>
60 p->dci->mod_name = "Sifive ECC Manager"; in ecc_register()
116 MODULE_AUTHOR("SiFive Inc.");
117 MODULE_DESCRIPTION("SiFive platform EDAC driver");
/linux/drivers/tty/serial/
H A Dsifive.c3 * SiFive UART driver
5 * Copyright (C) 2018-2019 SiFive
12 * - drivers/pwm/pwm-sifive.c
16 * SiFive FE310-G000 v2p3
18 * https://github.com/sifive/sifive-blocks/
20 * The SiFive UART design is not 8250-compatible. The following common
117 #define SIFIVE_SERIAL_NAME "sifive-serial"
119 /* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */
146 * Configuration data specific to this SiFive UART.
180 * __ssp_early_writel() - write to a SiFive serial port register (early)
[all …]
/linux/drivers/clk/sifive/
H A DKconfig4 bool "SiFive SoC driver support"
8 SoC drivers for SiFive Linux-capable SoCs.
13 tristate "PRCI driver for SiFive SoCs"
20 FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/
H A Dfu540-prci.h3 * Copyright (C) 2018-2021 SiFive, Inc.
8 * The FU540 PRCI implements clock and reset control for the SiFive
16 * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
25 #include <dt-bindings/clock/sifive-fu540-prci.h>
27 #include "sifive-prci.h"
/linux/tools/perf/pmu-events/arch/riscv/
H A Dmapfile.csv17 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core
18 0x489-0x8000000000000[1-9a-e]07-0x[78ac][[:xdigit:]]+,v1,sifive/bullet-07,core
19 0x489-0x8000000000000[1-9a-e]07-0xd[[:xdigit:]]+,v1,sifive/bullet-0d,core
20 0x489-0x8000000000000008-0x[[:xdigit:]]+,v1,sifive/p550,core
21 0x489-0x8000000000000[1-6]08-0x[9b][[:xdigit:]]+,v1,sifive/p650,core
/linux/arch/riscv/
H A DKconfig.vendor19 menu "SiFive" menu
21 bool "SiFive vendor extension support"
25 Say N here if you want to disable all SiFive vendor extension
26 support. This will cause any SiFive vendor extensions that are
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi19 compatible = "sifive,e51", "sifive,rocket0", "riscv";
40 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
71 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
102 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
133 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
210 compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
222 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
232 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
246 compatible = "microchip,mpfs-pdma", "sifive,pdma0";
/linux/drivers/spi/
H A Dspi-sifive.c3 // Copyright 2018 SiFive, Inc.
5 // SiFive SPI controller driver (master mode only)
7 // Author: SiFive, Inc.
8 // sifive@sifive.com
330 of_property_read_u32(pdev->dev.of_node, "sifive,fifo-depth", in sifive_spi_probe()
336 of_property_read_u32(pdev->dev.of_node, "sifive,max-bits-per-word", in sifive_spi_probe()
467 { .compatible = "sifive,spi0", },
483 MODULE_AUTHOR("SiFive, Inc. <sifive@sifive.com>");
484 MODULE_DESCRIPTION("SiFive SPI driver");
/linux/drivers/dma/sf-pdma/
H A Dsf-pdma.h3 * SiFive FU540 Platform DMA driver
4 * Copyright (C) 2019 SiFive
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf

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