| /linux-6.8/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/ |
| D | mmu.json | 45 "PublicDescrition": "Data-side S1 page walk cache lookup",
48 "BriefDescription": "Data-side S1 page walk cache lookup"
51 "PublicDescrition": "Data-side S1 page walk cache refill",
54 "BriefDescription": "Data-side S1 page walk cache refill"
57 "PublicDescrition": "Data-side S2 page walk cache lookup",
60 "BriefDescription": "Data-side S2 page walk cache lookup"
63 "PublicDescrition": "Data-side S2 page walk cache refill",
66 "BriefDescription": "Data-side S2 page walk cache refill"
69 "PublicDescription": "Data-side S1 table walk fault",
72 "BriefDescription": "Data-side S1 table walk fault"
[all …]
|
| /linux-6.8/Documentation/devicetree/bindings/interrupt-controller/ |
| D | fsl,mu-msi.yaml | 16 for one processor (A side) to signal the other processor (B side) using
20 different clocks (from each side of the different peripheral buses).
21 Therefore, the MU must synchronize the accesses from one side to the
23 registers (Processor A-side, Processor B-side).
40 - description: a side register base address
41 - description: b side register base address
45 - const: processor-a-side
46 - const: processor-b-side
49 description: a side interrupt number.
57 - description: a side power domain
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | translation.json | 29 …r chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request",
35 …r chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request",
41 …ion": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request",
47 …was loaded into the TLB from a location other than the local core's L2 due to a data side request",
53 …TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request",
59 …le Entry was loaded into the TLB from local core's L2 without conflict due to a data side request",
65 …ion": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request",
71 …ry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request",
77 …TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request",
83 …le Entry was loaded into the TLB from local core's L3 without conflict due to a data side request",
[all …]
|
| D | frontend.json | 293 …s L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
299 …s L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
305 …B from another chip's L4 on a different Node or Group (Distant) due to a instruction side request",
311 … from another chip's memory on the same Node or Group (Distant) due to a instruction side request",
317 …A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request",
323 …ded into the TLB from a location other than the local core's L2 due to a instruction side request",
329 …m local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request",
335 …y was loaded into the TLB from local core's L2 without conflict due to a instruction side request",
341 …A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request",
347 …ded into the TLB from a location other than the local core's L3 due to a instruction side request",
[all …]
|
| D | marked.json | 365 …s L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request",
371 …s L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request",
377 …B from another chip's L4 on a different Node or Group (Distant) due to a marked data side request",
383 … from another chip's memory on the same Node or Group (Distant) due to a marked data side request",
389 …A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request",
395 …ded into the TLB from a location other than the local core's L2 due to a marked data side request",
401 …m local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request",
407 …y was loaded into the TLB from local core's L2 without conflict due to a marked data side request",
413 …A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request",
419 …ded into the TLB from a location other than the local core's L3 due to a marked data side request",
[all …]
|
| /linux-6.8/drivers/char/hw_random/ |
| D | Kconfig | 28 This driver provides kernel-side support for a generic Random
43 This driver provides kernel-side support for the Random Number
57 This driver provides kernel-side support for the Random Number
70 This driver provides kernel-side support for the Random Number
82 This driver provides kernel-side support for the Random Number
94 This driver provides kernel-side support for the Random Number
107 This driver provides kernel-side support for the RNG200
121 This driver provides kernel-side support for the Random Number
134 This driver provides kernel-side support for the Random Number
147 This driver provides kernel-side support for the Random Number
[all …]
|
| /linux-6.8/Documentation/locking/ |
| D | seqlock.rst | 15 read side critical section is even and the same sequence count value is
17 be copied out inside the read side critical section. If the sequence
24 the end of the write side critical section the sequence count becomes
27 A sequence counter write side critical section must never be preempted
28 or interrupted by read side sections. Otherwise the reader will spin for
43 multiple writers. Write side critical sections must thus be serialized
48 write side section. If the read section can be invoked from hardirq or
76 /* ... [[write-side critical section]] ... */
85 /* ... [[read-side critical section]] ... */
95 As discussed at :ref:`seqcount_t`, sequence count write side critical
[all …]
|
| /linux-6.8/Documentation/usb/ |
| D | gadget_serial.rst | 57 side driver. It runs on a Linux system that has USB device side
66 | Host-Side CDC ACM USB Host |
78 | Device-Side | Gadget | Controller | |
84 On the device-side Linux system, the gadget serial driver looks
87 On the host-side system, the gadget serial device looks like a
92 The host side driver can potentially be any ACM compliant driver
98 With the gadget serial driver and the host side ACM or generic
100 the host and the gadget side systems as if they were connected by a
111 side kernel for "Support for USB Gadgets", for a "USB Peripheral
128 side Linux system. You can add this to the start up scripts, if
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/silvermont/ |
| D | virtual-memory.json | 12 "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)",
20 "BriefDescription": "Duration of D-side page-walks in core cycles",
23 …"PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk …
28 "BriefDescription": "D-side page-walks",
37 "BriefDescription": "Duration of I-side page-walks in core cycles",
40 …"PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fet…
45 "BriefDescription": "I-side page-walks",
54 "BriefDescription": "Total page walks that are completed (I-side and D-side)",
|
| /linux-6.8/Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 132 the ODT on the DRAM side and controller side are both disabled.
138 When the DRAM type is DDR3, this parameter defines the DRAM side drive
146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT
154 When the DRAM type is DDR3, this parameter defines the phy side CA line
162 When the DRAM type is DDR3, this parameter defines the PHY side DQ line
170 When the DRAM type is DDR3, this parameter defines the PHY side ODT
180 ODT on the DRAM side and controller side are both disabled.
186 When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
194 When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
202 When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
[all …]
|
| /linux-6.8/Documentation/RCU/ |
| D | checklist.rst | 18 tool for the job. Yes, RCU does reduce read-side overhead by
19 increasing write-side overhead, which is exactly why normal uses
28 read-side primitives is critically important.
59 2. Do the RCU read-side critical sections make proper use of
63 under your read-side code, which can greatly increase the
68 rcu_read_lock_sched(), or by the appropriate update-side lock.
77 Letting RCU-protected pointers "leak" out of an RCU read-side
81 *before* letting them out of the RCU read-side critical section.
158 perfectly legal (if redundant) for update-side code to
163 of an RCU read-side critical section. See lockdep.rst
[all …]
|
| D | lockdep.rst | 8 aware of when each task enters and leaves any flavor of RCU read-side
33 Check for RCU read-side critical section.
35 Check for RCU-bh read-side critical section.
37 Check for RCU-sched read-side critical section.
39 Check for SRCU read-side critical section.
83 1. An RCU read-side critical section (implicit), or
88 RCU read-side critical sections, in case (2) the ->file_lock prevents
99 complain even if this was used in an RCU read-side critical section unless
107 traversal primitives check for being called from within an RCU read-side
111 false and they are called from outside any RCU read-side critical section.
[all …]
|
| D | whatisRCU.rst | 103 b. Wait for all previous readers to complete their RCU read-side
166 reclaimer that the reader is entering an RCU read-side critical
167 section. It is illegal to block while in an RCU read-side
169 can preempt RCU read-side critical sections. Any RCU-protected
170 data structure accessed during an RCU read-side critical section
180 reclaimer that the reader is exiting an RCU read-side critical
181 section. Note that RCU read-side critical sections may be nested
190 all pre-existing RCU read-side critical sections on all CPUs
192 necessarily wait for any subsequent RCU read-side critical
206 read-side critical sections to complete, not necessarily for
[all …]
|
| /linux-6.8/include/linux/ |
| D | srcu.h | 83 * srcu_read_lock_held - might we be in SRCU read-side critical section?
87 * read-side critical section. In absence of CONFIG_DEBUG_LOCK_ALLOC,
88 * this assumes we are in an SRCU read-side critical section unless it can
109 * srcu_lock_sync(), which is basically an empty *write*-side critical section,
160 * really are in an SRCU read-side critical section.
161 * @c: condition to check for update-side use
163 * If PROVE_RCU is enabled, invoking this outside of an RCU read-side
176 * really are in an SRCU read-side critical section.
179 * is enabled, invoking this outside of an RCU read-side critical
188 * really are in an SRCU read-side critical section.
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/knightslanding/ |
| D | virtual-memory.json | 20 …"BriefDescription": "Counts the total number of core cycles for all the D-side page walks. The cyc…
27 …"BriefDescription": "Counts the total D-side page walks that are completed or started. The page wa…
35 …"BriefDescription": "Counts the total number of core cycles for all the I-side page walks. The cyc…
38 …"PublicDescription": "This event counts every cycle when an I-side (walks due to an instruction fe…
43 "BriefDescription": "Counts the total I-side page walks that are completed.",
51 "BriefDescription": "Counts the total page walks that are completed (I-side and D-side)",
|
| /linux-6.8/Documentation/RCU/Design/Requirements/ |
| D | Requirements.rst | 20 updaters do not block readers, which means that RCU's read-side
74 of all pre-existing RCU read-side critical sections. An RCU read-side
77 RCU treats a nested set as one big RCU read-side critical section.
131 | Second, even when using synchronize_rcu(), the other update-side |
173 The RCU read-side critical section in do_something_dlm() works with
190 In order to avoid fatal problems such as deadlocks, an RCU read-side
192 Similarly, an RCU read-side critical section must not contain anything
198 be good to be able to use RCU to coordinate read-side access to linked
370 outermost RCU read-side critical section containing that
387 #. Wait for all pre-existing RCU read-side critical sections to complete
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/powerpc/power9/ |
| D | translation.json | 25 …m another chip's memory on the same Node or Group (Distant) due to a data side request. When using…
35 …chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
60 … or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using…
75 …ared or modified data from another core's L2/L3 on the same chip due to a instruction side request"
100 …e TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request"
145 …from a memory location including L4 from local remote or distant due to a instruction side request"
150 …rom another core's L2/L3 on a different chip (remote or distant) due to a instruction side request"
165 … or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using…
185 …om another chip's L4 on a different Node or Group (Distant) due to a data side request. When using…
210 …chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
[all …]
|
| D | pipeline.json | 35 …her chip's L4 on a different Node or Group (Distant) due to a marked data side request. When using…
40 …s loaded into the TLB from local core's L2 without conflict due to a data side request. When using…
80 …ied (M) data from another core's L2 on the same chip due to a marked data side request. When using…
95 …h Modified (M) data from another core's L2 on the same chip due to a data side request. When using…
115 …e's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request. When using…
160 …core's L2/L3 on a different chip (remote or distant) due to a marked data side request. When using…
175 …ed into the TLB from local core's L3 with dispatch conflict due to a data side request. When using…
180 …d into the TLB from local core's L2 without conflict due to a marked data side request. When using…
225 …d into the TLB from local core's L3 without conflict due to a marked data side request. When using…
250 …s L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using…
[all …]
|
| D | pmc.json | 20 …on a different Node or Group (Distant), as this chip due to a marked data side request. When using…
30 …into the TLB from a location other than the local core's L3 due to a data side request. When using…
40 …e TLB from a location other than the local core's L2 due to a marked data side request.. When usin…
90 …a memory location including L4 from local remote or distant due to a data side request. When using…
95 … the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using…
100 …e Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using…
110 …ntry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using…
|
| /linux-6.8/drivers/nvme/target/ |
| D | Kconfig | 12 This enabled target side support for the NVMe protocol, that is
26 This enables target side NVMe passthru controller support for the
29 side, including executing Vendor Unique Commands.
40 to test NVMe host and target side features.
102 bool "NVMe over Fabrics In-band Authentication in target side"
107 target side.
|
| /linux-6.8/tools/perf/pmu-events/arch/arm64/ampere/ampereone/ |
| D | core-imp-def.json | 513 "PublicDescription": "L2 refill from I-side miss",
516 "BriefDescription": "L2 refill from I-side miss"
519 "PublicDescription": "L2 refill from D-side miss",
522 "BriefDescription": "L2 refill from D-side miss"
537 "PublicDescription": "D-side Stage1 tablewalk fault",
540 "BriefDescription": "D-side Stage1 tablewalk fault"
543 "PublicDescription": "D-side Stage2 tablewalk fault",
546 "BriefDescription": "D-side Stage2 tablewalk fault"
549 "PublicDescription": "D-side Tablewalk steps or descriptor fetches",
552 "BriefDescription": "D-side Tablewalk steps or descriptor fetches"
[all …]
|
| /linux-6.8/drivers/char/ipmi/ |
| D | Kconfig | 118 The driver implements the BMC side of the KCS contorller, it
119 provides the access of KCS IO space for BMC side.
130 The driver implements the BMC side of the KCS contorller, it
131 provides the access of KCS IO space for BMC side.
140 Provides a BMC-side character device implementing IPMI
171 implements the BMC side of the BT interface.
178 management (BMC) side.
180 The driver implements the BMC side of the SMBus system
|
| /linux-6.8/sound/pci/hda/ |
| D | Kconfig | 98 tristate "KUnit test for Cirrus side-codec library" if !KUNIT_ALL_TESTS
104 This builds KUnit tests for the cirrus side-codec library.
120 tristate "Build CS35L41 HD-audio side codec support for I2C Bus"
129 Say Y or M here to include CS35L41 I2C HD-audio side codec support
132 comment "Set to Y if you want auto-loading the side codec driver"
145 Say Y or M here to include CS35L41 SPI HD-audio side codec support
148 comment "Set to Y if you want auto-loading the side codec driver"
155 tristate "Build CS35L56 HD-audio side codec support for I2C Bus"
170 tristate "Build CS35L56 HD-audio side codec support for SPI Bus"
185 tristate "Build TAS2781 HD-audio side codec support for I2C Bus"
[all …]
|
| /linux-6.8/drivers/block/rnbd/ |
| D | README | 12 on the client side as local block devices.
26 Server side:
29 Client side:
39 mapped from the server side. After the session to the server machine is
40 established, the mapped device will appear on the client side under
51 to the block device on the server side by concatenating dev_search_path
73 information: side, max_hw_sectors, etc.
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/ivytown/ |
| D | uncore-cache.json | 201 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
210 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
219 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
228 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
237 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
246 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
255 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
264 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
273 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
282 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
[all …]
|