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Searched +full:sg2044 +full:- +full:pll (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/clk/sophgo/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
14 tristate "Sophgo SG2042 PLL clock support"
17 This driver supports the PLL clock controller on the
20 PLL, DDR PLL 0 and DDR PLL 1 respectively.
27 Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock
28 because it uses PLL clock
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_CLK_SOPHGO_CV1800) += clk-sophgo-cv1800.o
4 clk-sophgo-cv1800-y += clk-cv180
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H A Dclk-sg2044-pll.c1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2044 PLL clock controller driver
13 #include <linux/clk-provider.h>
22 #include <dt-bindings/clock/sophgo,sg2044-pll
85 struct sg2044_pll_internal pll; global() member
90 struct sg2044_clk_common * const *pll; global() member
142 struct sg2044_pll *pll = hw_to_sg2044_pll(hw); sg2044_pll_recalc_rate() local
263 struct sg2044_pll *pll = hw_to_sg2044_pll(hw); sg2044_pll_determine_rate() local
285 sg2044_pll_poll_update(struct sg2044_pll * pll) sg2044_pll_poll_update() argument
305 sg2044_pll_enable(struct sg2044_pll * pll,bool en) sg2044_pll_enable() argument
321 sg2044_pll_update_vcosel(struct sg2044_pll * pll,u64 rate) sg2044_pll_update_vcosel() argument
339 struct sg2044_pll *pll = hw_to_sg2044_pll(hw); sg2044_pll_set_rate() local
563 struct sg2044_pll *pll = hw_to_sg2044_pll(&common->hw); sg2044_pll_init_ctrl() local
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H A Dclk-sg2044.c1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2044 clock controller driver
13 #include <linux/clk-provider.h>
22 #include <dt-bindings/clock/sophgo,sg2044-clk.h>
81 struct sg2044_clk_common * const *pll; member
103 return (reg >> div->shif in sg2044_div_get_reg_div()
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/linux/Documentation/devicetree/bindings/soc/sophgo/
H A Dsophgo,sg2044-top-syscon.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2044-to
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/linux/drivers/soc/sophgo/
H A Dsg2044-topsys.c1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2044 multi-function system controller driver
16 .name = "sg2044-pll",
22 return devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO, in sg2044_topsys_probe()
29 { .compatible = "sophgo,sg2044
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
15 Power-on-Reset (PoR) sub-module, HW state machine to control chip
16 power-on, power-off and reset. Furthermore, the 8051 subsystem is
20 called cv1800-rtcsy
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/linux/Documentation/devicetree/bindings/clock/
H A Dsophgo,sg2044-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/sophgo,sg2044-cl
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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
7 #include <dt-bindings/clock/sophgo,sg2044-cl
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