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Searched +full:sg2042 +full:- +full:reset (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/Documentation/devicetree/bindings/reset/
Dsophgo,sg2042-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/sophgo,sg2042-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo SG2042 SoC Reset Controller
10 - Chen Wang <unicorn_wang@outlook.com>
14 const: sophgo,sg2042-reset
19 "#reset-cells":
23 - compatible
24 - reg
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/linux-6.15/arch/riscv/boot/dts/sophgo/
Dsg2042.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
13 #include "sg2042-cpus.dtsi"
16 compatible = "sophgo,sg2042";
17 #address-cells = <2>;
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/linux-6.15/Documentation/devicetree/bindings/pwm/
Dsophgo,sg2042-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/sophgo,sg2042-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo SG2042 PWM controller
10 - Chen Wang <unicorn_wang@outlook.com>
16 - $ref: pwm.yaml#
20 const: sophgo,sg2042-pwm
28 clock-names:
30 - const: apb
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/linux-6.15/drivers/pwm/
Dpwm-sophgo-sg2042.c1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2042 PWM Controller Driver
9 * - After reset, the output of the PWM channel is always high.
11 * - When HLPERIOD or PERIOD is reconfigured, PWM will start to
14 * - When PERIOD and HLPERIOD is set to 0, the PWM wave output will
17 * [1]:https://github.com/sophgo/sophgo-doc/tree/main/SG2042/TRM
27 #include <linux/reset.h>
47 * struct sg2042_pwm_ddata - private driver data
63 void __iomem *base = ddata->base; in pwm_sg2042_config()
76 if (state->polarity == PWM_POLARITY_INVERSED) in pwm_sg2042_apply()
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/linux-6.15/Documentation/hwmon/
Dsg2042-mcu.rst1 .. SPDX-License-Identifier: GPL-2.0
3 Kernel driver sg2042-mcu
8 * Onboard MCU for sg2042
10 Addresses scanned: -
12 Prefix: 'sg2042-mcu'
16 - Inochi Amaoto <inochiama@outlook.com>
19 -----------
25 -----------
27 This driver does not auto-detect devices. You will have to instantiate
29 Please see Documentation/i2c/instantiating-devices.rst for details.
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/linux-6.15/Documentation/devicetree/bindings/mmc/
Dsnps,dwcmshc-sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
16 - items:
17 - enum:
18 - rockchip,rk3528-dwcmshc
19 - rockchip,rk3562-dwcmshc
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/linux-6.15/drivers/clk/sophgo/
Dclk-sg2042-clkgen.c1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2042 Clock Generator Driver
12 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
19 #include "clk-sg2042.h"
23 #define R_PLL_STAT (0xC0 - R_PLL_BEGIN)
24 #define R_PLL_CLKEN_CONTROL (0xC4 - R_PLL_BEGIN)
25 #define R_MPLL_CONTROL (0xE8 - R_PLL_BEGIN)
26 #define R_FPLL_CONTROL (0xF4 - R_PLL_BEGIN)
27 #define R_DPLL0_CONTROL (0xF8 - R_PLL_BEGIN)
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/linux-6.15/drivers/reset/
Dreset-simple.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Simple Reset Controller Driver
7 * Based on Allwinner SoCs Reset Controller driver
11 * Maxime Ripard <maxime.ripard@free-electrons.com>
20 #include <linux/reset-controller.h>
21 #include <linux/reset/reset-simple.h>
40 spin_lock_irqsave(&data->lock, flags); in reset_simple_update()
42 reg = readl(data->membase + (bank * reg_width)); in reset_simple_update()
43 if (assert ^ data->active_low) in reset_simple_update()
47 writel(reg, data->membase + (bank * reg_width)); in reset_simple_update()
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/linux-6.15/drivers/mmc/host/
Dsdhci-of-dwcmshc.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/arm-smccc.h>
14 #include <linux/dma-mapping.h>
22 #include <linux/reset.h>
25 #include "sdhci-pltfm.h"
42 /* Tuning and auto-tuning fields in AT_CTRL_R control register */
52 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */
54 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */
119 #define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */
123 #define PHY_CNFG_PAD_SP_SG2042 0x09 /* PMOS TX drive strength for SG2042 */
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/linux-6.15/Documentation/devicetree/bindings/spi/
Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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