| /qemu/hw/gpio/ |
| H A D | aspeed_gpio.c | 32 * For each set of gpios there are three sensitivity registers that control
335 /* If the gpio is set to output... */ in aspeed_gpio_update()
338 ptrdiff_t set = aspeed_gpio_set_idx(s, regs); in aspeed_gpio_update() local
339 qemu_set_irq(s->gpios[set][gpio], !!(new & mask)); in aspeed_gpio_update()
387 * Once the source of a set is programmed, corresponding bits in the
392 * only bits 24, 16, 8, and 0 can be set
407 /* for each group in set */ in update_value_control_source()
422 /* Set ABCD */
437 /* Set EFGH */
452 /* Set IJKL */
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| /qemu/include/qapi/ |
| H A D | visitor-impl.h | 24 * be set for $TYPE visits to work"; if a visitor implementation omits
33 * permit some assertions based on whether a given bit is set (that
50 /* Must be set to visit structs */
57 /* Must be set to visit structs */
60 /* Must be set; implementations may require @list to be non-null,
65 /* Must be set */
71 /* Must be set */
74 /* Must be set by input and clone visitors to visit alternates */
82 /* Must be set */
86 /* Must be set */
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| /qemu/target/xtensa/core-de233_fpu/ |
| H A D | core-matmap.h | 157 * set = group of contiguous ways with exactly identical parameters
174 * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
194 #define XCHAL_ITLB_WAYS 7 /* number of ways (n-way set-associative TLB) */
198 /* Way set to which each way belongs: */
209 #define XCHAL_ITLB_ARF_SET0 0 /* index of n'th auto-refill set */
210 #define XCHAL_ITLB_ARF_SET1 1 /* index of n'th auto-refill set */
211 #define XCHAL_ITLB_ARF_SET2 2 /* index of n'th auto-refill set */
212 #define XCHAL_ITLB_ARF_SET3 3 /* index of n'th auto-refill set */
218 /* ITLB way set 0 (group of ways 0 thru 0): */
219 #define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
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| /qemu/ |
| H A D | meson.build | 398 # Choose instruction set (currently x86-only)
427 # add flags for individual instruction set extensions
445 # add required vector instruction set (each level implies those below)
651 # LIB_FUZZING_ENGINE was set; assume we are running on OSS-Fuzz, and
727 # Collect warning flags we want to set, sorted alphabetically
778 # Set up C++ compiler flags
1084 You probably need to set PKG_CONFIG_LIBDIR" to point
2325 config_host_data.set('CONFIG_HAVE_RUST', have_rust)
2340 config_host_data.set('CONFIG_AUDIO_' + k.to_upper(), v)
2364 config_host_data.set('CONFIG_AUDIO_DRIVERS',
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|
| H A D | .exrc | 3 "set secure
4 "set exrc
5 set expandtab
6 set shiftwidth=4
7 set smarttab
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| /qemu/libdecnumber/ |
| H A D | decNumber.c | 45 /* uint64_t types may be used. To avoid these, set DECUSE64=0 */
72 /* flag in the decContext is set (is 1). */
87 /* 7. Normally, input operands are assumed to be valid. Set DECCHECK */
96 /* is inappropriate for the operation and DECCHECK is not set. */
99 /* 8. Subset arithmetic is available only if DECSUBSET is set to 1. */
117 /* the call to set status may not return (if the handler uses long */
125 /* call decStatus even if traps are set in the context) and should */
179 #define DECVERB 1 /* set to 1 for verbose DECCHECK */
297 /* harness completes a set of tests). This checking may be unreliable */
367 /* set is the context for reporting errors */
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| /qemu/docs/system/devices/ |
| H A D | nvme.rst | 42 Set the maximum number of allowed I/O queue pairs. This replaces the
49 Set the Maximum Data Transfer Size of the device.
53 Vendor ID. Set this to ``on`` to revert to the unallocated Intel ID
85 Explicitly set the namespace identifier.
88 Set the UUID of the namespace. This will be reported as a "Namespace UUID"
92 Set the NGUID of the namespace. This will be reported as a "Namespace Globally
99 Set the EUI-64 of the namespace. This will be reported as a "IEEE Extended
129 subsystem. If set to ``off``, the namespace will remain a private namespace
135 If set to ``on``, the namespace will be be available in the subsystem, but
136 not attached to any controllers initially. A shared namespace with this set
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| /qemu/linux-headers/linux/ |
| H A D | vhost.h | 29 /* Set current process as the (exclusive) owner of this file descriptor. This
37 /* Set up/modify memory layout */
43 * The bit is set using an atomic 32 bit operation. */
44 /* Set base address for logging. */
69 /* Set number of descriptors in ring. This parameter can not
72 /* Set addresses for the ring. */
79 /* Set the vring byte order in num. Valid values are VHOST_VRING_LITTLE_ENDIAN
84 * set.
86 * support SET also support GET.
108 /* Set eventfd to poll for added buffers */
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| /qemu/docs/specs/ |
| H A D | acpi_cpu_hotplug.rst | 23 with GPE.2 event set. CPU present map is read by ACPI BIOS GPE.2 handler
44 - read accesses return all bits set to 0.
79 It's valid only when bit 0 is set.
87 if set to 1, OSPM requests firmware to perform device eject.
125 if set to 1 clears device insert event, set by OSPM
129 if set to 1 clears device remove event, set by OSPM
133 if set to 1 initiates device eject, set by OSPM when it
135 when bit #4 is set. In case bit #4 were set, it's cleared as
138 if set to 1, OSPM hands over device eject to firmware.
158 following writes to 'Command data' register set OST event
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| /qemu/target/ppc/ |
| H A D | trace-events | 4 kvm_failed_spr_set(int spr, const char *msg) "Warning: Unable to set SPR %d to KVM: %s"
6 kvm_failed_fpscr_set(const char *msg) "Unable to set FPSCR to KVM: %s"
7 kvm_failed_fp_set(const char *fpname, int fpnum, const char *msg) "Unable to set %s%d to KVM: %s"
8 kvm_failed_vscr_set(const char *msg) "Unable to set VSCR to KVM: %s"
9 kvm_failed_vr_set(int vr, const char *msg) "Unable to set VR%d to KVM: %s"
17 kvm_failed_vpa_addr_set(const char *msg) "Unable to set VPA address to KVM: %s"
18 kvm_failed_slb_set(const char *msg) "Unable to set SLB shadow state to KVM: %s"
19 kvm_failed_dtl_set(const char *msg) "Unable to set dispatch trace log state to KVM: %s"
20 kvm_failed_null_vpa_addr_set(const char *msg) "Unable to set VPA address to KVM: %s"
21 kvm_failed_put_vpa(void) "Warning: Unable to set VPA information to KVM"
|
| /qemu/include/exec/ |
| H A D | tlb-flags.h | 30 * Invalid is set when the page does not have requested permissions.
31 * MMIO is set when we want the target helper to use the functional
42 * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x].
45 /* Set if TLB entry requires byte swap. */
47 /* Set if TLB entry contains a watchpoint. */
49 /* Set if TLB entry requires aligned accesses. */
51 /* Set if TLB entry writes ignored. */
53 /* Set if TLB entry is an IO callback. */
69 /* Set if TLB entry references a clean RAM page. */
71 /* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
|
| /qemu/include/hw/xen/interface/ |
| H A D | features.h | 16 * The list of all the features the guest supports. They are set by
24 * XENFEAT_dom0 MUST be set if the guest is to be booted as dom0,
28 * If set, the guest does not need to write-protect its pagetables, and can
34 * If set, the guest does not need to write-protect its segment descriptor
40 * If set, translation between the guest's 'pseudo-physical' address space
47 /* If set, the guest is running in supervisor mode (e.g., x86 ring 0). */
51 * If set, the guest does not need to allocate x86 PAE page directories
63 * If set, GNTTABOP_map_grant_ref honors flags to be placed into guest kernel
92 * x86/PVH: If set, ACPI RSDP can be placed at any address. Otherwise RSDP
103 * XENFEAT_direct_mapped is set; otherwise XENFEAT_not_direct_mapped
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| /qemu/contrib/plugins/ |
| H A D | cache.c | 37 * A CacheSet is a set of cache blocks. A memory block that maps to a set can be
38 * put in any of the blocks inside the set. The number of block per set is
45 * In order to search for memory data in the cache, the set identifier and tag
46 * are extracted from the address and the set is probed to see whether a tag
50 * the set number, and the tag.
52 * The set number is used to identify the set in which the block may exist.
53 * The tag is compared against all the tags of a set to search for a match. If a
92 void (*update_hit)(Cache *cache, int set, int blk);
93 void (*update_miss)(Cache *cache, int set, int blk);
127 * LRU evection policy: For each set, a generation counter is maintained
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| /qemu/docs/devel/testing/ |
| H A D | ci-jobs.rst.inc | 8 Set variable globally in the user's CI namespace
11 Variables can be set globally in the user's CI namespace setting.
13 For further information about how to set these variables, please refer to::
17 Set variable manually when pushing a branch or tag to the user's repository
20 Variables can be set manually when pushing a branch or tag, using
29 For further information about how to set these variables, please refer to::
69 * QEMU_CI_nnn - variables to be set by contributors in their
91 The following variables may be set when defining a job in the
137 The following variables may be set by contributors to control
146 Set this variable to 1 to create the pipelines, but leave all
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| /qemu/python/qemu/utils/ |
| H A D | qom.py | 4 usage: qom [-h] {set,get,list,tree,fuse} ...
12 {set,get,list,tree,fuse}
13 set Set a QOM property value
30 # Based on ./scripts/qmp/qom-[set|get|tree|list]
51 QOM Command - Set a property to a given value.
53 usage: qom-set [-h] [--socket SOCKET] <path>.<property> <value>
55 Set a QOM property value
65 set via QMP_SOCKET environment variable.
67 name = 'set'
68 help = 'Set a QOM property value'
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| /qemu/tests/tcg/aarch64/gdbstub/ |
| H A D | test-mte.py | 8 # The test consists in breaking just after a tag is set in a specific memory
9 # chunk, and then using the GDB 'memory-tagging' subcommands to set/get tags in
63 # Test allocation tag 'set and print' commands. Commands on logical
66 # Set the allocation tag for the first granule (16 bytes) of
68 gdb.execute(f"memory-tag set-allocation-tag {ta} 1 04", False, True)
70 # Then set the allocation tag for the second granule to a known
72 # set correctly and don't run over each other.
73 gdb.execute(f"memory-tag set-allocation-tag {ta}+16 1 06", False, True)
84 report(True, "Allocation tags are correctly set/printed.")
86 report(False, "Can't set/print allocation tags!")
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| /qemu/docs/system/arm/ |
| H A D | virt.rst | 108 Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
112 Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
116 Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
120 Set ``on``/``off`` to enable/disable placing devices and RAM in physical
126 a CPU type which implements LPAE, you will need to manually set
131 Set ``on``/``off`` to enable/disable the compact layout for high memory regions.
135 Set ``on``/``off`` to enable/disable the high memory region for GICv3 or
140 Set ``on``/``off`` to enable/disable the high memory region for PCI ECAM.
144 Set ``on``/``off`` to enable/disable the high memory region for PCI MMIO.
148 Set the high memory region size for PCI MMIO. Must be a power of 2 and
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| /qemu/util/ |
| H A D | event.c | 8 * - FREE -> SET (qemu_event_set)
9 * - BUSY -> SET (qemu_event_set)
10 * - SET -> FREE (qemu_event_reset)
14 * BUSY -> SET and FREE -> BUSY, respectively.
16 * Without futex, BUSY -> SET and FREE -> BUSY never happen. Instead, the waking
17 * operation follows FREE -> SET and the blocking operation will happen in
18 * qemu_event_wait() if the event is not SET.
20 * SET->BUSY does not happen (it can be observed from the outside but
21 * it really is SET->FREE->BUSY).
23 * busy->free provably cannot happen; to enforce it, the set->free transition
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| /qemu/linux-user/alpha/ |
| H A D | signal.c | 70 abi_ulong frame_addr, target_sigset_t *set) in setup_sigcontext() argument
75 __put_user(set->sig[0], &sc->sc_mask); in setup_sigcontext()
126 target_sigset_t *set, CPUAlphaState *env) in setup_frame() argument
138 setup_sigcontext(&frame->sc, env, frame_addr, set); in setup_frame()
164 target_sigset_t *set, CPUAlphaState *env) in setup_rt_frame() argument
180 __put_user(set->sig[0], &frame->uc.tuc_osf_sigmask); in setup_rt_frame()
184 setup_sigcontext(&frame->uc.tuc_mcontext, env, frame_addr, set); in setup_rt_frame()
186 __put_user(set->sig[i], &frame->uc.tuc_sigmask.sig[i]); in setup_rt_frame()
214 sigset_t set; in do_sigreturn() local
223 target_to_host_sigset_internal(&set, &target_set); in do_sigreturn()
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| /qemu/tests/tcg/aarch64/system/ |
| H A D | mte.S | 28 * Set MAIR_EL1 (Memory Attribute Index Register). In boot.S, the
29 * attribute index for .mte_page is set to point to MAILR_EL field Attr1
30 * (AttrIndx=Attr1), so set Attr1 as Tagged Normal (MTE) to enable MTE
40 * Set TCR_EL1 (Translation Control Registers) to ignore the top byte
50 * Set SCTLR_EL1 (System Control Register) to enable the use of MTE
77 * Set GCR for random tag generation. 0xA5 is just a random value to set
92 * set the allocation tag for granule at 'addr'. The tag is extracted
101 * set the same, otherwise something is off and the test fails -- an
|
| /qemu/include/hw/ |
| H A D | qdev-properties.h | 8 * @set_default: true if the default value should be set from @defval,
10 * (if false then no default value is set by the property system
42 ObjectPropertyAccessor *set; member
111 * The default value is set in instance_init().
133 * When the array property is set, the @_field member of the device
134 * struct is set to the array length, and @_arrayfield is set to point
175 * Set properties between creation and realization.
183 * Set properties between creation and realization.
184 * @value must be valid. Each property may be set at most once.
236 * of @source can set them.
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| /qemu/linux-headers/asm-mips/ |
| H A D | kvm.h | 53 * bits[31..16] - Register set.
55 * Register set = 0: GP registers from kvm_regs (see definitions below).
57 * Register set = 1: CP0 registers.
58 * bits[15..8] - COP0 register set.
60 * COP0 register set = 0: Main CP0 registers.
64 * COP0 register set = 1: MAARs.
67 * Register set = 2: KVM specific registers (see definitions below).
69 * Register set = 3: FPU / MSA registers (see definitions below).
71 * Other sets registers may be added in the future. Each set would
138 * DC: Set 0: Master disable CP0_Count and set COUNT_RESUME to now
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| /qemu/tests/qemu-iotests/ |
| H A D | 039 | 61 # The dirty bit must not be set
75 # The dirty bit must be set
84 # The dirty bit must be set
92 # The dirty bit must not be set
110 # The dirty bit must be set
115 # The dirty bit must not be set
128 # The dirty bit must not be set since lazy_refcounts=off
143 # The dirty bit must not be set
161 # The dirty bit must be set
173 # The dirty bit must not be set
|
| H A D | common.qemu | 51 # If $silent is set to anything but an empty string, then
53 # If $mismatch_only is set, only non-matching responses will
61 # If $only_capture_events is set to anything but an empty string,
65 # If $success_or_failure is set, the meaning of the arguments is
68 # success and ${QEMU_STATUS[$1]} is set to 0.
71 # is not set) or ${QEMU_STATUS[$1]} is set to -1 (otherwise).
161 # Set qemu_cmd_repeat to the number of times to repeat the cmd
162 # until either timeout, or a response. If it is not set, or <=0,
165 # If neither $silent nor $mismatch_only is set, and $cmd begins with '{',
168 # If $qemu_error_no_exit is set, then even if the expected response
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| /qemu/tests/tcg/multiarch/ |
| H A D | late-attach.c | 15 sigset_t set; in main() local
18 assert(sigfillset(&set) == 0); in main()
19 assert(sigprocmask(SIG_BLOCK, &set, NULL) == 0); in main()
24 assert(sigwait(&set, &sig) == 0); in main()
32 assert(sigpending(&set) == 0); in main()
34 if (sigismember(&set, sig)) { in main()
|