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/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Drenesas,intc-irqpin.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - enum:
16 - renesas,intc-irqpin-r8a7740 # R-Mobile A1
17 - renesas,intc-irqpin-r8a7778 # R-Car M1A
18 - renesas,intc-irqpin-r8a7779 # R-Car H1
19 - renesas,intc-irqpin-sh73a0 # SH-Mobile AG5
[all …]
/linux-5.10/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
15 /* COM Temperature Sense Reset Bitfield Definitions */
21 /* COM Temperature Sense Power Down Bitfield Definitions */
27 /* COM Temperature Sense Ready Bitfield Definitions */
33 /* COM Temperature Sense Ready Latch High Bitfield Definitions */
39 /* COM Temperature Sense Data Out [B:0] Bitfield Definitions */
50 /* register address for bitfield rx dma good octet counter lsw [1f:0] */
52 /* register address for bitfield rx dma good packet counter lsw [1f:0] */
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/linux-5.10/drivers/irqchip/
Dirq-renesas-intc-irqpin.c1 // SPDX-License-Identifier: GPL-2.0
36 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
37 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
38 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
39 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
40 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
42 * (*) May be accessed by more than one driver instance - lock needed
43 * (**) Read-modify-write access by one driver instance - lock needed
44 * (***) Accessed by one driver instance only - no locking needed
51 int width; member
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/linux-5.10/drivers/clk/bcm/
Dclk-kona-setup.c18 #include "clk-kona.h"
21 #define selector_clear_exists(sel) ((sel)->width = 0)
28 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
31 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
34 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
37 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
40 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
43 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
53 struct peri_clk_data *peri = bcm_clk->u.peri; in clk_requires_trigger()
57 if (bcm_clk->type != bcm_clk_peri) in clk_requires_trigger()
[all …]
Dclk-kona.c15 #include "clk-kona.h"
20 #include <linux/clk-provider.h>
33 /* Bitfield operations */
35 /* Produces a mask of set bits covering a range of a 32-bit value */
36 static inline u32 bitfield_mask(u32 shift, u32 width) in bitfield_mask() argument
38 return ((1 << width) - 1) << shift; in bitfield_mask()
41 /* Extract the value of a bitfield found within a given register value */
42 static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width) in bitfield_extract() argument
44 return (reg_val & bitfield_mask(shift, width)) >> shift; in bitfield_extract()
47 /* Replace the value of a bitfield found within a given register value */
[all …]
/linux-5.10/drivers/gpu/drm/panfrost/
Dpanfrost_gpu.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/bitfield.h>
8 #include <linux/dma-mapping.h>
35 dev_warn(pfdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx\n", in panfrost_gpu_irq_handler()
40 dev_warn(pfdev->dev, "There were multiple GPU faults - some have not been reported\n"); in panfrost_gpu_irq_handler()
65 ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, in panfrost_gpu_soft_reset()
69 dev_err(pfdev->dev, "gpu soft reset timed out\n"); in panfrost_gpu_soft_reset()
82 * The Amlogic integrated Mali-T820, Mali-G31 & Mali-G52 needs in panfrost_gpu_amlogic_quirk()
129 /* Limit read & write ID width for AXI */ in panfrost_gpu_init_quirks()
141 pfdev->features.revision >= 0x2000) in panfrost_gpu_init_quirks()
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/linux-5.10/include/linux/ssb/
Dssb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
108 #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
144 #define SSB_IDLOW_CCW 0x000C0000 /* Cycle counter width */
168 * in two-byte quantities.
202 #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
218 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
219 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
225 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
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/linux-5.10/Documentation/hwmon/
Dsysfs-interface.rst5 through the sysfs interface. Since lm-sensors 3.0.0, libsensors is
6 completely chip-independent. It assumes that all the kernel drivers
10 This is a major improvement compared to lm-sensors 2.
16 before they make full sense. For example, most chips can only measure
22 For this reason, even if we aim at a chip-independent libsensors, it will
37 Up to lm-sensors 3.0.0, libsensors looks for hardware monitoring attributes
38 in the "physical" device directory. Since lm-sensors 3.0.1, attributes found
61 to cause an alarm) is chip-dependent.
68 -------------------------------------------------------------------------
71 `[0-*]` denotes any positive number starting from 0
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/linux-5.10/include/xen/interface/
Dxen.h86 /* Architecture-specific hypercall definitions. */
100 * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a
101 * global VIRQ. The former can be bound once per VCPU and cannot be re-bound.
103 * allocated to VCPU0 but can subsequently be re-bound.
119 /* Architecture-specific VIRQ definitions. */
144 * x != 0 => PFD == x - 1
146 * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command.
147 * -------------
155 * ptr[:2] -- Machine address of the page-table entry to modify.
156 * val -- Value to write.
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/linux-5.10/arch/arm/boot/dts/
Dr8a7778.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M1A (R8A77781) SoC
14 #include <dt-bindings/clock/r8a7778-clock.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
20 interrupt-parent = <&gic>;
21 #address-cells = <1>;
22 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
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Dr8a7779.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H1 (R8A77790) SoC
9 #include <dt-bindings/clock/r8a7779-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7779-sysc.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
21 #address-cells = <1>;
[all …]
/linux-5.10/include/uapi/linux/
Dvideodev2.h1 /* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) */
5 * Copyright (C) 1999-2012 the contributors
47 * All kernel-specific stuff were moved to media/v4l2-dev.h, so
66 #include <linux/v4l2-common.h>
67 #include <linux/v4l2-controls.h>
80 /* Four-character-code (FOURCC) */
98 buffer, top-bottom order */
99 V4L2_FIELD_SEQ_BT = 6, /* same as above + bottom-top order */
205 /* Obsolete pre-1998 SMPTE 240M HDTV standard, superseded by Rec 709 */
218 * NTSC 1953 colorspace. This only makes sense when dealing with
[all …]
/linux-5.10/drivers/mmc/host/
Dcavium.c9 * Copyright (C) 2012-2017 Cavium Inc.
16 #include <linux/bitfield.h>
18 #include <linux/dma-direction.h>
19 #include <linux/dma-mapping.h>
23 #include <linux/mmc/slot-gpio.h>
46 * being used. However, non-MMC devices like SD use command and
128 cr = cvm_mmc_cr_types + (cmd->opcode & 0x3f); in cvm_mmc_get_cr_mods()
129 hardware_ctype = cr->ctype; in cvm_mmc_get_cr_mods()
130 hardware_rtype = cr->rtype; in cvm_mmc_get_cr_mods()
131 if (cmd->opcode == MMC_GEN_CMD) in cvm_mmc_get_cr_mods()
[all …]
/linux-5.10/drivers/net/ethernet/cadence/
Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
107 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
108 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
109 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
110 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
111 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
119 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
128 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
129 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
[all …]
/linux-5.10/drivers/media/i2c/
Dadv7511-v4l2.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * This file is named adv7511-v4l2.c so it doesn't conflict with the Analog
23 #include <linux/v4l2-dv-timings.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-common.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-dv-timings.h>
33 MODULE_PARM_DESC(debug, "debug level (0-2)");
100 /* Did we receive hotplug and rx-sense signals? */
153 return &container_of(ctrl->handler, struct adv7511_state, hdl)->sd; in to_sd()
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/linux-5.10/drivers/net/phy/
Dmarvell.c1 // SPDX-License-Identifier: GPL-2.0+
33 #include <linux/bitfield.h>
317 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in marvell_config_intr()
369 err = marvell_set_polarity(phydev, phydev->mdix_ctrl); in marvell_config_aneg()
384 if (phydev->autoneg != AUTONEG_ENABLE || changed) { in marvell_config_aneg()
434 * marvell,reg-init property stored in the of_node for the phydev.
436 * marvell,reg-init = <reg-page reg mask value>,...;
438 * There may be one or more sets of <reg-page reg mask value>:
440 * reg-page: which register bank to use.
442 * mask: if non-zero, ANDed with existing register value.
[all …]
/linux-5.10/fs/ntfs/
Dlayout.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * layout.h - All NTFS associated on-disk structures. Part of the Linux-NTFS
6 * Copyright (c) 2001-2005 Anton Altaparmakov
71 approx. 4.7x10^21 bytes. (-; */
117 * operator! (-8
163 * been written to disk. The values 0 and -1 (ie. 0xffff) are not used. All
170 * (obviously) finish before the last le16 of the first 512-byte sector.
175 NTFS_RECORD_TYPE magic; /* A four-byte magic identifying the record
212 FILE_BadClus = 8, /* Contains all bad clusters in the non-resident
223 FILE_reserved12 = 12, /* Reserved for future use (records 12-15). */
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/linux-5.10/drivers/gpu/drm/radeon/
Dr300_reg.h95 /* State based - direct writes to registers trigger vertex
107 /* index size - when not set the indices are assumed to be 16 bit */
147 /* BEGIN: Vertex data assembly - lots of uncertainties */
207 * - always set up to produce at least two attributes:
209 * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
307 /* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
308 * plane is per-pixel and the second plane is per-vertex.
330 # define R300_2288_R300 0x00750000 /* -- nh */
331 # define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
381 /* These are values from r300_reg/r300_reg.h - they are known to be correct
[all …]
/linux-5.10/Documentation/virt/kvm/
Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
13 - System ioctls: These query and set global attributes which affect the
17 - VM ioctls: These query and set attributes that affect an entire virtual
24 - vcpu ioctls: These query and set attributes that control the operation
32 - device ioctls: These query and set attributes that control the operation
80 facility that allows backward-compatible extensions to the API to be
104 the ioctl returns -ENOTTY.
122 -----------------------
139 -----------------
[all …]
/linux-5.10/drivers/net/wireless/ath/ath10k/
Dmac.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
15 #include <linux/bitfield.h>
24 #include "wmi-tlv.h"
25 #include "wmi-ops.h"
87 #define ath10k_a_rates_size (ARRAY_SIZE(ath10k_rates) - \
122 for (i = 0; i < sband->n_bitrates; i++) { in ath10k_mac_hw_rate_to_idx()
123 rate = &sband->bitrates[i]; in ath10k_mac_hw_rate_to_idx()
[all …]
/linux-5.10/Documentation/
Dmemory-barriers.txt19 documentation at tools/memory-model/. Nevertheless, even this memory
37 Note also that it is possible that a barrier may be a no-op for an
48 - Device operations.
49 - Guarantees.
53 - Varieties of memory barrier.
54 - What may not be assumed about memory barriers?
55 - Data dependency barriers (historical).
56 - Control dependencies.
57 - SMP barrier pairing.
58 - Examples of memory barrier sequences.
[all …]
/linux-5.10/drivers/scsi/mpt3sas/
Dmpt3sas_scsih.c5 * Copyright (C) 2012-2014 LSI Corporation
6 * Copyright (C) 2013-2014 Avago Technologies
7 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
22 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
41 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
93 static u8 scsi_io_cb_idx = -1;
94 static u8 tm_cb_idx = -1;
95 static u8 ctl_cb_idx = -1;
96 static u8 base_cb_idx = -1;
97 static u8 port_enable_cb_idx = -1;
[all …]
/linux-5.10/drivers/gpu/drm/i915/
Di915_reg.h18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
28 #include <linux/bitfield.h>
44 * registers that are defined solely for the use by function-like macros.
52 * should be defined using function-like macros.
58 * with underscore, followed by a function-like macro choosing the right
68 * function-like macros may be used to define bit fields, but do note that the
87 * Try to re-use existing register macro definitions. Only add new macros for
120 * REG_BIT() - Prepare a u32 bit value
121 * @__n: 0-based bit number
133 * REG_GENMASK() - Prepare a continuous u32 bitmask
[all …]
/linux-5.10/net/wireless/
Dnl80211.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * This is the new netlink-based wireless configuration interface.
5 * Copyright 2006-2010 Johannes Berg <johannes@sipsolutions.net>
6 * Copyright 2013-2014 Intel Mobile Communications GmbH
7 * Copyright 2015-2017 Intel Deutschland GmbH
8 * Copyright (C) 2018-2020 Intel Corporation
32 #include "rdev-ops.h"
50 NL80211_MCGRP_TESTMODE /* keep last - ifdef! */
74 int wiphy_idx = -1; in __cfg80211_wdev_from_attrs()
75 int ifidx = -1; in __cfg80211_wdev_from_attrs()
[all …]
/linux-5.10/drivers/net/ethernet/chelsio/cxgb4/
Dt4_hw.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
43 * t4_wait_op_done_val - wait until an operation is completed
46 * @mask: a single-bit field within @reg that indicates completion
55 * operation completes and -EAGAIN otherwise.
68 if (--attempts == 0) in t4_wait_op_done_val()
69 return -EAGAIN; in t4_wait_op_done_val()
83 * t4_set_reg_field - set a register field to a value
102 * t4_read_indirect - read indirectly addressed registers
[all …]

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