| /linux-5.10/arch/arm/mach-lpc32xx/ |
| D | suspend.S | 2 * arch/arm/mach-lpc32xx/suspend.S
41 stmfd r0!, {r3 - r7, sp, lr}
65 @ Setup self-refresh with support for manual exit of
66 @ self-refresh mode
72 @ Wait for self-refresh acknowledge, clocks to the DRAM device
73 @ will automatically stop on start of self-refresh
78 bne 3b @ Branch until self-refresh mode starts
80 @ Enter direct-run mode from run mode
115 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
116 @ update yet. DRAM is still in self-refresh
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| D | pm.c | 2 * arch/arm/mach-lpc32xx/pm.c
17 * direct-run, and halt modes. When switching between halt and run modes,
18 * the CPU transistions through direct-run mode. For Linux, direct-run
27 * Direct-run mode:
38 * wake the system up back into direct-run mode.
40 * DRAM refresh
41 * DRAM clocking and refresh are slightly different for systems with DDR
43 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
44 * a transition to direct-run mode will stop all DDR accesses (no clocks).
46 * and exit DRAM self-refresh modes must not be executed in DRAM. A small
[all …]
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| /linux-5.10/drivers/gpu/drm/ |
| D | drm_self_refresh_helper.c | 1 // SPDX-License-Identifier: MIT
27 * framework to implement panel self refresh (SR) support. Drivers are
31 * &drm_connector_state.self_refresh_aware to true at runtime if it is SR-aware
32 * (meaning it knows how to initiate self refresh on the panel).
38 * that tells you to disable/enable SR on the panel instead of power-cycling it.
72 struct drm_crtc *crtc = sr_data->crtc; in drm_self_refresh_helper_entry_work()
73 struct drm_device *dev = crtc->dev; in drm_self_refresh_helper_entry_work()
85 ret = -ENOMEM; in drm_self_refresh_helper_entry_work()
90 state->acquire_ctx = &ctx; in drm_self_refresh_helper_entry_work()
98 if (!crtc_state->enable) in drm_self_refresh_helper_entry_work()
[all …]
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| /linux-5.10/arch/arm/mach-socfpga/ |
| D | self-refresh.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014-2015 Altera Corporation. All rights reserved.
32 .arch armv7-a
44 * return value: lower 16 bits: loop count going into self refresh
45 * upper 16 bits: loop count exiting self refresh
53 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
89 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
109 * Shift loop count for exiting self refresh into upper 16 bits.
110 * Leave loop count for requesting self refresh in lower 16 bits.
125 .word . - socfpga_sdram_self_refresh
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| D | pm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-socfpga/pm.c
5 * Copyright (C) 2014-2015 Altera Corporation. All rights reserved.
7 * with code from pm-imx6.c
8 * Copyright 2011-2014 Freescale Semiconductor, Inc.
35 np = of_find_compatible_node(NULL, NULL, "mmio-sram"); in socfpga_setup_ocram_self_refresh()
37 pr_err("%s: Unable to find mmio-sram in dtb\n", __func__); in socfpga_setup_ocram_self_refresh()
38 return -ENODEV; in socfpga_setup_ocram_self_refresh()
44 ret = -ENODEV; in socfpga_setup_ocram_self_refresh()
48 ocram_pool = gen_pool_get(&pdev->dev, NULL); in socfpga_setup_ocram_self_refresh()
[all …]
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| /linux-5.10/arch/arm/mach-pxa/ |
| D | sleep.S | 2 * Low-level PXA250/210 sleep/wakeUp support
18 #include <mach/pxa2xx-regs.h>
27 * pxa3xx_finish_suspend() - forces CPU into sleep state (S2D3C4)
54 @ prepare SDRAM refresh settings
58 @ enable SDRAM self-refresh mode
61 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
95 @ prepare SDRAM refresh settings
99 @ enable SDRAM self-refresh mode
106 @ We keep the change-down close to the actual suspend on SDRAM
107 @ as possible to eliminate messing about with the refresh clock
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| /linux-5.10/drivers/cpuidle/ |
| D | cpuidle-zynq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013 Xilinx
7 * based on arch/arm/mach-at91/cpuidle.c
9 * The cpu idle uses wait-for-interrupt and RAM self refresh in order
10 * to implement two idle states -
11 * #1 wait-for-interrupt
12 * #2 wait-for-interrupt and RAM self refresh
28 /* Add code for DDR self refresh start */ in zynq_enter_idle()
44 .desc = "WFI and RAM Self Refresh",
61 .name = "cpuidle-zynq",
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| D | cpuidle-at91.c | 2 * based on arch/arm/mach-kirkwood/cpuidle.c
10 * The cpu idle uses wait-for-interrupt and RAM self refresh in order
11 * to implement two idle states -
12 * #1 wait-for-interrupt
13 * #2 wait-for-interrupt and RAM self refresh
46 .desc = "WFI and DDR Self Refresh",
54 at91_standby = (void *)(dev->dev.platform_data); in at91_cpuidle_probe()
61 .name = "cpuidle-at91",
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| D | cpuidle-kirkwood.c | 8 * The cpu idle uses wait-for-interrupt and DDR self refresh in order
9 * to implement two idle states -
10 * #1 wait-for-interrupt
11 * #2 wait-for-interrupt and DDR self refresh
50 .desc = "WFI and DDR Self Refresh",
84 MODULE_ALIAS("platform:kirkwood-cpuidle");
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| /linux-5.10/arch/sh/boards/mach-kfr2r09/ |
| D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * KFR2R09 sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
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| /linux-5.10/arch/sh/boards/mach-migor/ |
| D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Migo-R sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* SBSC: disable power down and put in self-refresh mode */
42 /* SBSC: set auto-refresh mode */
51 mov #-1, r4
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| /linux-5.10/arch/sh/boards/mach-ap325rxa/ |
| D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * AP325RXA sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* SBSC: disable power down and put in self-refresh mode */
42 /* SBSC: set auto-refresh mode */
51 mov #-1, r4
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| /linux-5.10/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 4 - compatible: Must be "rockchip,rk3399-dmc".
5 - devfreq-events: Node to get DDR loading, Refer to
7 rockchip-dfi.txt
8 - clocks: Phandles for clock specified in "clock-names" property
9 - clock-names : The name of clock used by the DFI, must be
11 - operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp.txt
13 - center-supply: DMC supply node.
14 - status: Marks the node enabled/disabled.
17 - interrupts: The CPU interrupt number. The interrupt specifier
21 - rockchip,pmu: Phandle to the syscon managing the "PMU general register
[all …]
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| /linux-5.10/arch/sh/boards/mach-ecovec24/ |
| D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Ecovec24 sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* DBSC: put memory in self-refresh mode */
41 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
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| /linux-5.10/arch/sh/kernel/cpu/shmobile/ |
| D | pm.c | 1 // SPDX-License-Identifier: GPL-2.0
28 * Sleep Self-Refresh mode is above plus RAM put in Self-Refresh
29 * Standby Self-Refresh mode is above plus stopped clocks
37 * U-standby mode is unsupported since it needs bootloader hacks
62 /* Let assembly snippet in on-chip memory handle the rest */ in sh_mobile_call_standby()
88 sdp->addr.stbcr = 0xa4150020; /* STBCR */ in sh_mobile_register_self_refresh()
89 sdp->addr.bar = 0xa4150040; /* BAR */ in sh_mobile_register_self_refresh()
90 sdp->addr.pteh = 0xff000000; /* PTEH */ in sh_mobile_register_self_refresh()
91 sdp->addr.ptel = 0xff000004; /* PTEL */ in sh_mobile_register_self_refresh()
92 sdp->addr.ttb = 0xff000008; /* TTB */ in sh_mobile_register_self_refresh()
[all …]
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| /linux-5.10/arch/sh/boards/mach-se/7724/ |
| D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * MS7724SE sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
72 /* DBSC: re-initialize and put in auto-refresh */
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| /linux-5.10/include/soc/at91/ |
| D | at91sam9_sdramc.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
8 * SDRAM Controllers (SDRAMC) - System peripherals registers.
26 #define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
27 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
54 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
57 #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
62 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
63 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
74 #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
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| D | at91sam9_ddrsdr.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 #define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
22 #define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
59 #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
63 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
64 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
65 #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
74 #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
81 #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
[all …]
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| /linux-5.10/arch/arm/mach-at91/ |
| D | pm_suspend.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-at91/pm_slow_clock.S
13 #include "pm_data-offsets.h"
77 /* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
81 stmfd sp!, {r4 - r12, lr}
111 /* Active the self-refresh mode */
135 /* Exit the self-refresh mode */
140 ldmfd sp!, {r4 - r12, pc}
274 /* Switch the main clock source to 12-MHz RC oscillator */
511 * - MAINCK if using ULP0 fast variant
[all …]
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| /linux-5.10/arch/arm/mach-imx/ |
| D | suspend-imx53.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
60 /* Set FDVFS bit of M4IF_MCR0 to request DDR to enter self-refresh */
66 /* Poll FDVACK bit of M4IF_MCR to wait for DDR to enter self-refresh */
115 /* Clear FDVFS bit of M4IF_MCR0 to request DDR to exit self-refresh */
121 /* Poll FDVACK bit of M4IF_MCR to wait for DDR to exit self-refresh */
134 .word . - imx53_suspend
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| /linux-5.10/arch/arm/mach-omap2/ |
| D | sleep24xx.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mach-omap2/sleep.S
7 * Richard Woodruff <r-woodruff2@ti.com>
26 * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
31 * R0 : DLL ctrl value pre-Sleep
40 * For less than 242x-ES2.2 upon wake from a sleep mode where the external
41 * oscillator was stopped, a timing bug exists where a non-stabilized 12MHz
53 stmfd sp!, {r0 - r12, lr} @ save registers on stack
59 orr r4, r4, #0x40 @ enable self refresh on idle req
69 /* The DPLL has to be on before we take the DDR out of self refresh */
[all …]
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| /linux-5.10/arch/mips/alchemy/common/ |
| D | sleeper.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
104 sw zero, 0x0020(a0) /* Auto Refresh */
130 sw zero, 0x08d0(a0) /* Self Refresh */
133 /* wait for sdram to enter self-refresh mode */
189 /* auto refresh */
200 /* issue the Self Refresh command */
206 /* wait for sdram to enter self-refresh mode */
240 * the write-only Config[OD] bit and set it back to one...
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| /linux-5.10/arch/sh/include/asm/ |
| D | suspend.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
31 #define SH_MOBILE_POST(x) (-(x))
33 /* board code registration function for self-refresh assembly snippets */
58 /* data area for low-level sleep code */
63 /* addresses of board specific self-refresh snippets */
90 #define SUSP_SH_STANDBY (1 << 1) /* SH-Mobile Software standby mode */
91 #define SUSP_SH_RSTANDBY (1 << 2) /* SH-Mobile R-standby mode */
92 #define SUSP_SH_USTANDBY (1 << 3) /* SH-Mobile U-standby mode */
93 #define SUSP_SH_SF (1 << 4) /* Enable self-refresh */
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| /linux-5.10/drivers/staging/olpc_dcon/ |
| D | TODO | 2 - complete rewrite:
5 2. The dcon low-power display mode can then be integrated using the
6 drm damage tracking and self-refresh helpers.
7 This bolted-on self-refresh support that digs around in fbdev
9 - see if vx855 gpio API can be made similar enough to cs5535 so we can
12 Please send patches to Greg Kroah-Hartman <greg@kroah.com> and
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| /linux-5.10/arch/arm/mach-tegra/ |
| D | sleep-tegra20.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
15 #include <asm/proc-fns.h>
79 * puts the specified CPU in wait-for-event mode on the flow controller
85 * corrupts r0-r3, r12
140 * Switches the CPU cluster to PLL-P and enters sleep.
157 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLP,
218 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
242 * puts memory in self-refresh for LP0 and LP1
318 * puts sdram in self refresh
[all …]
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