| /linux-6.8/Documentation/devicetree/bindings/usb/ |
| D | usb251xb.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip USB 2.0 Hi-Speed Hub Controller
10 - Richard Leitner <richard.leitner@skidata.com>
15 - microchip,usb2422
16 - microchip,usb2512b
17 - microchip,usb2512bi
18 - microchip,usb2513b
19 - microchip,usb2513bi
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| /linux-6.8/Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
26 clock-names:
28 - const: dmc_clk
30 operating-points-v2: true
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| /linux-6.8/include/soc/at91/ |
| D | sama7-ddr.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
33 #define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
34 #define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
35 #define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */
38 #define DDR3PHY_DXCCR_DXPDR (1 << 3) /* Data Power Down Receiver */
41 #define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */
44 #define DDR3PHY_ZQ0SR0_PDO_OFF (0) /* Pull-down output impedance select offset */
45 #define DDR3PHY_ZQ0SR0_PUO_OFF (5) /* Pull-up output impedance select offset */
46 #define DDR3PHY_ZQ0SR0_PDODT_OFF (10) /* Pull-down on-die termination impedance select offset */
47 #define DDR3PHY_ZQ0SRO_PUODT_OFF (15) /* Pull-up on-die termination impedance select offset */
[all …]
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| D | at91sam9_ddrsdr.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
63 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
64 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
65 #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
68 #define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "F…
69 #define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "…
73 #define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
74 #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
80 #define AT91_DDRSDRC_LPDDR2_PWOFF (1 << 3) /* LPDDR Power Off */
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| D | at91sam9_sdramc.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
8 * SDRAM Controllers (SDRAMC) - System peripherals registers.
54 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
56 #define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
57 #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
62 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
63 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
65 #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
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| /linux-6.8/tools/crypto/ccp/ |
| D | test_dbc.py | 2 # SPDX-License-Identifier: GPL-2.0
25 def system_is_secured() -> bool:
34 def __init__(self, data) -> None: argument
35 self.d = None
36 self.signature = b"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
37 self.uid = b"1111111111111111"
40 def setUp(self) -> None: argument
41 self.d = open(DEVICE_NODE)
44 def tearDown(self) -> None: argument
45 if self.d:
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| /linux-6.8/scripts/gdb/linux/ |
| D | genpd.py | 1 # SPDX-License-Identifier: GPL-2.0
25 if dev['power']['runtime_error']:
27 if dev['power']['disable_depth']:
35 return _RPM_STATUS_LOOKUP[dev['power']['runtime_status']]
43 def __init__(self): argument
44 super(LxGenPDSummary, self).__init__('lx-genpd-summary', gdb.COMMAND_DATA)
46 def summary_one(self, genpd): argument
50 status_string = 'off-{}'.format(genpd['state_idx'])
59 gdb.write('%-30s %-15s %s\n' % (
70 gdb.write(' %-50s %s\n' % (kobj_path, rtpm_status_str(dev)))
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| /linux-6.8/drivers/usb/host/ |
| D | ohci-omap.c | 1 // SPDX-License-Identifier: GPL-1.0+
6 * (C) Copyright 2000-2005 David Brownell
7 * (C) Copyright 2002 Hewlett-Packard Company
13 * and on ohci-sa1111.c by Christopher Hoover <ch@hpl.hp.com>
19 #include <linux/dma-mapping.h>
28 #include <linux/platform_data/usb-omap1.h>
29 #include <linux/soc/ti/omap1-usb.h>
30 #include <linux/soc/ti/omap1-mux.h>
31 #include <linux/soc/ti/omap1-soc.h>
32 #include <linux/soc/ti/omap1-io.h>
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| D | ohci-s3c2410.c | 1 // SPDX-License-Identifier: GPL-1.0+
6 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 * (C) Copyright 2002 Hewlett-Packard Company
14 * Modified for S3C2410 from ohci-sa1111.c, ohci-omap.c and ohci-lh7a40.c
28 #include <linux/platform_data/usb-ohci-s3c2410.h>
55 return dev_get_platdata(hcd->self.controller); in to_s3c2410_info()
60 struct s3c2410_hcd_info *info = dev_get_platdata(&dev->dev); in s3c2410_start_hc()
62 dev_dbg(&dev->dev, "s3c2410_start_hc:\n"); in s3c2410_start_hc()
70 info->hcd = hcd; in s3c2410_start_hc()
71 info->report_oc = s3c2410_hcd_oc; in s3c2410_start_hc()
[all …]
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| D | ehci-fsl.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2005-2009 MontaVista Software, Inc.
8 * Power Management support by Dave Liu <daveliu@freescale.com>,
9 * Jerry Huang <Chang-Ming.Huang@freescale.com> and
29 #include "ehci-fsl.h"
32 #define DRV_NAME "fsl-ehci"
40 * fsl_ehci_drv_probe - initialize FSL-based HCDs
56 pr_debug("initializing FSL-SOC USB Controller\n"); in fsl_ehci_drv_probe()
59 pdata = dev_get_platdata(&pdev->dev); in fsl_ehci_drv_probe()
61 dev_err(&pdev->dev, in fsl_ehci_drv_probe()
[all …]
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| D | ohci-at91.c | 1 // SPDX-License-Identifier: GPL-1.0+
6 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
11 * Based on ohci-omap.c
16 #include <linux/arm-smccc.h>
18 #include <linux/dma-mapping.h>
30 #include <soc/at91/atmel-sfr.h>
40 ((struct ohci_at91_priv *)hcd_to_ohci(h)->priv)
57 bool wakeup; /* Saved wake-up state for resume */
71 /*-------------------------------------------------------------------------*/
75 if (ohci_at91->clocked) in at91_start_clock()
[all …]
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| /linux-6.8/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/ |
| D | ali_drw.json | 24 "BriefDescription": "A Read-Modify-Write Op at HIF interface. The unit is 64B.",
136 "BriefDescription": "A read-write turnaround.",
150 "BriefDescription": "A Write-After-Read hazard.",
157 "BriefDescription": "A Read-After-Write hazard.",
164 "BriefDescription": "A Write-After-Write hazard.",
171 "BriefDescription": "Rank0 enters self-refresh(SRE).",
178 "BriefDescription": "Rank1 enters self-refresh(SRE).",
185 "BriefDescription": "Rank2 enters self-refresh(SRE).",
192 "BriefDescription": "Rank3 enters self-refresh(SRE).",
199 "BriefDescription": "Rank0 enters power-down(PDE).",
[all …]
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| /linux-6.8/arch/arm/mach-socfpga/ |
| D | self-refresh.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014-2015 Altera Corporation. All rights reserved.
32 .arch armv7-a
44 * return value: lower 16 bits: loop count going into self refresh
45 * upper 16 bits: loop count exiting self refresh
48 /* Enable dynamic clock gating in the Power Control Register. */
53 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
89 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
109 * Shift loop count for exiting self refresh into upper 16 bits.
110 * Leave loop count for requesting self refresh in lower 16 bits.
[all …]
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| /linux-6.8/arch/arm/mach-at91/ |
| D | pm_suspend.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-at91/pm_slow_clock.S
13 #include "pm_data-offsets.h"
16 .arch armv7-a
91 * Set state for 2.5V low power regulator
92 * @ena: 0 - disable regulator
93 * 1 - enable regulator
125 * Enable self-refresh
164 /* Switch to self-refresh. */
170 /* Wait for self-refresh enter. */
[all …]
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| /linux-6.8/arch/arm/mach-lpc32xx/ |
| D | pm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-lpc32xx/pm.c
12 * LPC32XX CPU and system power management
14 * The LPC32XX has three CPU modes for controlling system power: run,
15 * direct-run, and halt modes. When switching between halt and run modes,
16 * the CPU transistions through direct-run mode. For Linux, direct-run
25 * Direct-run mode:
36 * wake the system up back into direct-run mode.
41 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
42 * a transition to direct-run mode will stop all DDR accesses (no clocks).
[all …]
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| /linux-6.8/drivers/media/usb/cx231xx/ |
| D | cx231xx-pcb-cfg.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 cx231xx-pcb-cfg.h - driver for Conexant
87 Sound-IF Signals present */
93 SELF_POWER = 0x0, /* 0: self power */
94 BUS_POWER = 0x40 /* 1: bus power */
172 u8 type; /* bus power or self power,
173 self power--0, bus_power--1 */
174 u8 speed; /* usb speed, 2.0--1, 1.1--0 */
176 u32 ts1_source; /* three source -- BDA,External,encode */
179 u8 digital_index; /* bus-power used */
[all …]
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| /linux-6.8/drivers/gpu/drm/ |
| D | drm_self_refresh_helper.c | 1 // SPDX-License-Identifier: MIT
27 * framework to implement panel self refresh (SR) support. Drivers are
31 * &drm_connector_state.self_refresh_aware to true at runtime if it is SR-aware
32 * (meaning it knows how to initiate self refresh on the panel).
38 * that tells you to disable/enable SR on the panel instead of power-cycling it.
42 * &drm_crtc_state.self_refresh_active if they want to enter low power mode
72 struct drm_crtc *crtc = sr_data->crtc; in drm_self_refresh_helper_entry_work()
73 struct drm_device *dev = crtc->dev; in drm_self_refresh_helper_entry_work()
85 ret = -ENOMEM; in drm_self_refresh_helper_entry_work()
90 state->acquire_ctx = &ctx; in drm_self_refresh_helper_entry_work()
[all …]
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| /linux-6.8/drivers/staging/iio/accel/ |
| D | adis16203.c | 1 // SPDX-License-Identifier: GPL-2.0+
22 /* Output, power supply */
31 /* Output, x-axis inclination */
34 /* Output, y-axis inclination */
58 /* General-purpose digital input/output control */
81 /* Self-test at power-on: 1 = disabled, 0 = enabled */
87 /* Self-test enable */
90 /* Data-ready enable: 1 = enabled, 0 = disabled */
93 /* Data-ready polarity: 1 = active high, 0 = active low */
96 /* Data-ready line selection: 1 = DIO1, 0 = DIO0 */
[all …]
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| /linux-6.8/rust/kernel/ |
| D | allocator.rs | 1 // SPDX-License-Identifier: GPL-2.0
16 /// - `ptr` can be either null or a pointer which has been allocated by this allocator.
17 /// - `new_layout` must have a non-zero size.
18 unsafe fn krealloc_aligned(ptr: *mut u8, new_layout: Layout, flags: bindings::gfp_t) -> *mut u8 { in krealloc_aligned()
26 // to use the "power-of-two" size/alignment guarantee (see comments in `kmalloc()` for in krealloc_aligned()
35 // - `ptr` is either null or a pointer returned from a previous `k{re}alloc()` by the in krealloc_aligned()
37 // - `size` is greater than 0 since it's either a `layout.size()` (which cannot be zero in krealloc_aligned()
43 unsafe fn alloc(&self, layout: Layout) -> *mut u8 { in alloc() argument
44 // SAFETY: `ptr::null_mut()` is null and `layout` has a non-zero size by the function safety in alloc()
49 unsafe fn dealloc(&self, ptr: *mut u8, _layout: Layout) { in dealloc() argument
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| /linux-6.8/tools/power/pm-graph/ |
| D | sleepgraph.py | 2 # SPDX-License-Identifier: GPL-2.0-only
21 # https://01.org/pm-graph
23 # git@github.com:intel/pm-graph
51 # ----------------- LIBRARIES --------------------
73 print('[%09.3f] %s' % (time.time()-mystarttime, msg))
81 # ----------------- CLASSES --------------------
85 # A global, single-instance container used to
107 cgtest = -1
125 epath = '/sys/kernel/tracing/events/power/'
126 pmdpath = '/sys/power/pm_debug_messages'
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| /linux-6.8/Documentation/devicetree/bindings/mfd/ |
| D | x-powers,axp152.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/x-powers,axp152.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: X-Powers AXP PMIC
10 - Chen-Yu Tsai <wens@csie.org>
13 - if:
18 - x-powers,axp152
19 - x-powers,axp202
20 - x-powers,axp209
[all …]
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| /linux-6.8/Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
36 - At the time this documentation was written, the debug driver mainly relies on
[all …]
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| /linux-6.8/arch/sh/boards/mach-migor/ |
| D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Migo-R sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* SBSC: disable power down and put in self-refresh mode */
42 /* SBSC: set auto-refresh mode */
51 mov #-1, r4
|
| /linux-6.8/arch/sh/boards/mach-ap325rxa/ |
| D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * AP325RXA sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* SBSC: disable power down and put in self-refresh mode */
42 /* SBSC: set auto-refresh mode */
51 mov #-1, r4
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| /linux-6.8/drivers/crypto/intel/qat/qat_common/ |
| D | adf_gen4_hw_data.c | 1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
90 csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr; in adf_gen4_init_hw_csr_ops()
91 csr_ops->read_csr_ring_head = read_csr_ring_head; in adf_gen4_init_hw_csr_ops()
92 csr_ops->write_csr_ring_head = write_csr_ring_head; in adf_gen4_init_hw_csr_ops()
93 csr_ops->read_csr_ring_tail = read_csr_ring_tail; in adf_gen4_init_hw_csr_ops()
94 csr_ops->write_csr_ring_tail = write_csr_ring_tail; in adf_gen4_init_hw_csr_ops()
95 csr_ops->read_csr_e_stat = read_csr_e_stat; in adf_gen4_init_hw_csr_ops()
96 csr_ops->write_csr_ring_config = write_csr_ring_config; in adf_gen4_init_hw_csr_ops()
97 csr_ops->write_csr_ring_base = write_csr_ring_base; in adf_gen4_init_hw_csr_ops()
98 csr_ops->write_csr_int_flag = write_csr_int_flag; in adf_gen4_init_hw_csr_ops()
[all …]
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