Searched full:sbr (Results 1 – 17 of 17) sorted by relevance
| /linux-6.8/Documentation/devicetree/bindings/memory-controllers/ |
| D | snps,dw-umctl2-ddrc.yaml | 70 enum: [ pclk, aclk, core, sbr ]
82 enum: [ prst, arst, core, sbr ]
115 clock-names = "pclk", "aclk", "core", "sbr";
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| /linux-6.8/drivers/infiniband/hw/hfi1/ |
| D | pcie.c | 768 * before the SBR for the Pcie Gen3.
792 * Trigger a secondary bus reset (SBR) on ourselves using our parent.
818 * This is an end around to do an SBR during probe time. A new API needs in trigger_sbr()
1011 /* hold the SBus resource across the firmware download and SBR */ in do_pcie_gen3_transition()
1047 * will be performed automatically after the SBR when the target in do_pcie_gen3_transition()
1247 /* hold DC in reset across the SBR */ in do_pcie_gen3_transition()
1250 /* save firmware control across the SBR */ in do_pcie_gen3_transition()
1265 * step 7: initiate the secondary bus reset (SBR) in do_pcie_gen3_transition()
1280 "%s: read of VendorID failed after SBR, err %d\n", in do_pcie_gen3_transition()
1286 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); in do_pcie_gen3_transition()
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| D | chip.h | 722 #define SBUS_TIMEOUT 4000 /* long enough for a FW download and SBR */
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| /linux-6.8/drivers/tty/serial/ |
| D | fsl_lpuart.c | 1986 unsigned int sbr, brfa; in lpuart_set_termios() local
2104 sbr = sport->port.uartclk / (16 * baud); in lpuart_set_termios()
2105 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; in lpuart_set_termios()
2107 bdh |= (sbr >> 8) & 0x1F; in lpuart_set_termios()
2112 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); in lpuart_set_termios()
2134 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; in __lpuart32_serial_setbrg() local
2144 * Baud Rate = baud clock / ((OSR+1) × SBR) in __lpuart32_serial_setbrg()
2148 sbr = 0; in __lpuart32_serial_setbrg()
2151 /* calculate the temporary sbr value */ in __lpuart32_serial_setbrg()
2158 * osr and sbr values in __lpuart32_serial_setbrg()
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| /linux-6.8/arch/mips/include/asm/ |
| D | bmips-spaces.h | 5 /* Avoid collisions with system base register (SBR) region on BMIPS3300 */
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| /linux-6.8/arch/mips/include/asm/mach-bmips/ |
| D | spaces.h | 13 /* Avoid collisions with system base register (SBR) region on BMIPS3300 */
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| /linux-6.8/sound/soc/intel/atom/ |
| D | sst-mfld-dsp.h | 337 u8 bdownsample; /*SBR downsampling 0 - disable 1 -enabled AAC+ only */
341 u8 sbr_signalling;/*disable/enable/set automode the SBR tool.AAC+*/
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| /linux-6.8/drivers/media/i2c/ |
| D | tc358746.c | 951 * sbr - source_bitrate in bits/s in tc358746_link_validate()
954 * image-width / csir >= (image-width - fifo-sz) / sbr in tc358746_link_validate()
955 * image-width * sbr / csir >= image-width - fifo-sz in tc358746_link_validate()
956 * fifo-sz >= image-width - image-width * sbr / csir; with n = csir/sbr in tc358746_link_validate()
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| /linux-6.8/drivers/gpu/drm/amd/pm/swsmu/inc/ |
| D | amdgpu_smu.h | 1328 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR.
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| /linux-6.8/arch/arm64/boot/dts/apple/ |
| D | t8103-pmgr.dtsi | 15 label = "sbr";
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| D | t8112-pmgr.dtsi | 15 label = "sbr";
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| /linux-6.8/drivers/pci/controller/dwc/ |
| D | pcie-tegra194.c | 383 /* SBR & Surprise Link Down WAR */ in tegra_pcie_rp_irq_handler()
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| /linux-6.8/drivers/acpi/ |
| D | scan.c | 1312 acpi_has_method(handle, "SBR") && in acpi_ibm_smbus_match()
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| /linux-6.8/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_device.c | 1318 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
3053 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */ in amdgpu_device_ip_late_init()
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| /linux-6.8/include/linux/ |
| D | pci.h | 1509 /* Temporary until new and working PCI SBR API in place */
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| /linux-6.8/drivers/scsi/ |
| D | advansys.c | 2031 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2032 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
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| /linux-6.8/drivers/pci/ |
| D | quirks.c | 3736 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
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