| /linux-6.15/Documentation/devicetree/bindings/memory-controllers/ |
| D | snps,dw-umctl2-ddrc.yaml | 70 enum: [ pclk, aclk, core, sbr ]
82 enum: [ prst, arst, core, sbr ]
115 clock-names = "pclk", "aclk", "core", "sbr";
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| /linux-6.15/drivers/infiniband/hw/hfi1/ |
| D | pcie.c | 768 * before the SBR for the Pcie Gen3.
792 * Trigger a secondary bus reset (SBR) on ourselves using our parent.
818 * This is an end around to do an SBR during probe time. A new API needs in trigger_sbr()
1011 /* hold the SBus resource across the firmware download and SBR */ in do_pcie_gen3_transition()
1047 * will be performed automatically after the SBR when the target in do_pcie_gen3_transition()
1233 /* hold DC in reset across the SBR */ in do_pcie_gen3_transition()
1236 /* save firmware control across the SBR */ in do_pcie_gen3_transition()
1251 * step 7: initiate the secondary bus reset (SBR) in do_pcie_gen3_transition()
1266 "%s: read of VendorID failed after SBR, err %d\n", in do_pcie_gen3_transition()
1272 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); in do_pcie_gen3_transition()
[all …]
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| D | chip.h | 722 #define SBUS_TIMEOUT 4000 /* long enough for a FW download and SBR */
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| /linux-6.15/drivers/tty/serial/ |
| D | fsl_lpuart.c | 1993 unsigned int sbr, brfa; in lpuart_set_termios() local
2111 sbr = port->uartclk / (16 * baud); in lpuart_set_termios()
2112 brfa = ((port->uartclk - (16 * sbr * baud)) * 2) / baud; in lpuart_set_termios()
2114 bdh |= (sbr >> 8) & 0x1F; in lpuart_set_termios()
2119 writeb(sbr & 0xFF, port->membase + UARTBDL); in lpuart_set_termios()
2141 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, baud; in __lpuart32_serial_setbrg() local
2151 * Baud Rate = baud clock / ((OSR+1) × SBR) in __lpuart32_serial_setbrg()
2155 sbr = 0; in __lpuart32_serial_setbrg()
2158 /* calculate the temporary sbr value */ in __lpuart32_serial_setbrg()
2165 * osr and sbr values in __lpuart32_serial_setbrg()
[all …]
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| /linux-6.15/arch/mips/include/asm/ |
| D | bmips-spaces.h | 5 /* Avoid collisions with system base register (SBR) region on BMIPS3300 */
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| /linux-6.15/arch/mips/include/asm/mach-bmips/ |
| D | spaces.h | 13 /* Avoid collisions with system base register (SBR) region on BMIPS3300 */
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| /linux-6.15/sound/soc/intel/atom/ |
| D | sst-mfld-dsp.h | 337 u8 bdownsample; /*SBR downsampling 0 - disable 1 -enabled AAC+ only */
341 u8 sbr_signalling;/*disable/enable/set automode the SBR tool.AAC+*/
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| /linux-6.15/drivers/media/i2c/ |
| D | tc358746.c | 477 * sbr - source_bitrate in bits/s in tc358746_calc_vb_size()
480 * image-width / csir >= (image-width - fifo-sz) / sbr in tc358746_calc_vb_size()
481 * image-width * sbr / csir >= image-width - fifo-sz in tc358746_calc_vb_size()
482 * fifo-sz >= image-width - image-width * sbr / csir; with n = csir/sbr in tc358746_calc_vb_size()
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| /linux-6.15/drivers/scsi/mpt3sas/ |
| D | mpt3sas_ctl.h | 459 * struct mpt3_enable_diag_sbr_reload - enable sbr reload
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| D | mpt3sas_ctl.c | 2611 * _ctl_enable_diag_sbr_reload - enable sbr reload bit
2615 * Enable the SBR reload bit
2652 ioc_err(ioc, "%s: Failed to set Diag SBR Reload Bit\n", __func__); in _ctl_enable_diag_sbr_reload()
2656 ioc_info(ioc, "%s: Successfully set the Diag SBR Reload Bit\n", __func__); in _ctl_enable_diag_sbr_reload()
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| /linux-6.15/drivers/cxl/ |
| D | pci.c | 1102 * registers. SBR, however, will wipe all device configurations. in cxl_reset_done()
1109 dev_crit(dev, "SBR happened without memory regions removal.\n"); in cxl_reset_done()
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| /linux-6.15/drivers/platform/x86/intel/pmc/ |
| D | lnl.c | 348 {"SBR", 0, 1},
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| /linux-6.15/arch/arm64/boot/dts/apple/ |
| D | s8001-pmgr.dtsi | 58 label = "sbr";
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| D | t8011-pmgr.dtsi | 67 label = "sbr";
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| D | s800-0-3-pmgr.dtsi | 58 label = "sbr";
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| D | t8010-pmgr.dtsi | 58 label = "sbr";
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| D | t8012-pmgr.dtsi | 66 label = "sbr";
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| D | t8015-pmgr.dtsi | 94 label = "sbr";
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| D | t8112-pmgr.dtsi | 15 label = "sbr";
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| D | t8103-pmgr.dtsi | 15 label = "sbr";
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| /linux-6.15/drivers/net/ethernet/mellanox/mlxsw/ |
| D | pci.c | 1804 goto sbr; in mlxsw_pci_reset_at_pci_disable()
1813 sbr: in mlxsw_pci_reset_at_pci_disable()
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| /linux-6.15/drivers/pci/ |
| D | pci.c | 5068 * Per CXL spec r3.1, sec 8.1.5.2, when "Unmask SBR" is 0, the SBR in cxl_sbr_masked()
5070 * hot reset when the SBR bit is set to 1. in cxl_sbr_masked()
5084 * If "dev" is below a CXL port that has SBR control masked, SBR in pci_reset_bus_function()
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| /linux-6.15/drivers/gpu/drm/amd/pm/swsmu/inc/ |
| D | amdgpu_smu.h | 1355 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR.
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| /linux-6.15/drivers/pci/controller/dwc/ |
| D | pcie-tegra194.c | 372 /* SBR & Surprise Link Down WAR */ in tegra_pcie_rp_irq_handler()
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| /linux-6.15/drivers/acpi/ |
| D | scan.c | 1373 acpi_has_method(handle, "SBR") && in acpi_ibm_smbus_match()
|