Searched +full:sa8775p +full:- +full:ctcu (Results 1 – 2 of 2) sorted by relevance
| /linux-6.15/Documentation/devicetree/bindings/arm/ |
| D | qcom,coresight-ctcu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/qcom,coresight-ctcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yuanfang Zhang <quic_yuanfang@quicinc.com>
11 - Mao Jinlong <quic_jinlmao@quicinc.com>
12 - Jie Gan <quic_jiegan@quicinc.com>
30 - qcom,sa8775p-ctcu
38 clock-names:
40 - const: apb
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| /linux-6.15/drivers/hwtracing/coresight/ |
| D | coresight-ctcu-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
19 #include "coresight-ctcu.h"
20 #include "coresight-priv.h"
22 DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu");
24 #define ctcu_writel(drvdata, val, offset) __raw_writel((val), drvdata->base + offset)
25 #define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base + offset)
30 * ATID register is 32 bits. Therefore, an ETR device has a 128-bit long field
31 * in CTCU. Each trace ID is represented by one bit in that filed.
34 * ------------------------------------------------------
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