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/linux-6.15/arch/riscv/boot/dts/starfive/
Djh7100.dtsi220 resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
250 rstgen: reset-controller@11840000 { label
267 resets = <&rstgen JH7100_RSTN_I2C0_APB>;
280 resets = <&rstgen JH7100_RSTN_I2C1_APB>;
293 resets = <&rstgen JH7100_RSTN_GPIO_APB>;
307 resets = <&rstgen JH7100_RSTN_UART2_APB>;
320 resets = <&rstgen JH7100_RSTN_UART3_APB>;
333 resets = <&rstgen JH7100_RSTN_I2C2_APB>;
346 resets = <&rstgen JH7100_RSTN_I2C3_APB>;
359 resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
[all …]
/linux-6.15/Documentation/devicetree/bindings/hwmon/
Dstarfive,jh71x0-temp.yaml67 resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
68 <&rstgen JH7100_RSTN_TEMP_APB>;
/linux-6.15/arch/riscv/boot/dts/sophgo/
Dsg2042.dtsi59 resets = <&rstgen RST_I2C0>;
72 resets = <&rstgen RST_I2C1>;
85 resets = <&rstgen RST_I2C2>;
98 resets = <&rstgen RST_I2C3>;
174 resets = <&rstgen RST_PWM>;
520 rstgen: reset-controller@7030013000 { label
536 resets = <&rstgen RST_UART0>;
/linux-6.15/Documentation/devicetree/bindings/clock/
Dnvidia,tegra20-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
25 RSTGEN provides the registers needed to control resetting of each block in
Dnvidia,tegra124-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
25 RSTGEN provides the registers needed to control resetting of each block in
/linux-6.15/Documentation/devicetree/bindings/reset/
Dsophgo,sg2042-reset.yaml31 rstgen: reset-controller@c00 {
/linux-6.15/Documentation/devicetree/bindings/pwm/
Dsophgo,sg2042-pwm.yaml57 resets = <&rstgen RST_PWM>;
Dopencores,pwm.yaml54 resets = <&rstgen 109>;