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/qemu/tests/tcg/multiarch/
H A Dsha512.c261 /** One round of SHA-512. */
262 static void Round(uint64_t a, uint64_t b, uint64_t c, uint64_t *d, uint64_t e, uint64_t f, uint64_t… in Round() function
276 Round(a, b, c, &d, e, f, g, &h, 0x428a2f98d728ae22ull, w0 = be64_to_cpu(chunk[0])); in Transform()
277 Round(h, a, b, &c, d, e, f, &g, 0x7137449123ef65cdull, w1 = be64_to_cpu(chunk[1])); in Transform()
278 Round(g, h, a, &b, c, d, e, &f, 0xb5c0fbcfec4d3b2full, w2 = be64_to_cpu(chunk[2])); in Transform()
279 Round(f, g, h, &a, b, c, d, &e, 0xe9b5dba58189dbbcull, w3 = be64_to_cpu(chunk[3])); in Transform()
280 Round(e, f, g, &h, a, b, c, &d, 0x3956c25bf348b538ull, w4 = be64_to_cpu(chunk[4])); in Transform()
281 Round(d, e, f, &g, h, a, b, &c, 0x59f111f1b605d019ull, w5 = be64_to_cpu(chunk[5])); in Transform()
282 Round(c, d, e, &f, g, h, a, &b, 0x923f82a4af194f9bull, w6 = be64_to_cpu(chunk[6])); in Transform()
283 Round(b, c, d, &e, f, g, h, &a, 0xab1c5ed5da6d8118ull, w7 = be64_to_cpu(chunk[7])); in Transform()
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H A Dtest-aes-main.c.inc38 } Round;
40 static const Round rounds[] = {
41 /* Round 1 */
57 { { 0xa0, 0xfa, 0xfe, 0x17, /* round key */
62 /* Round 2 */
78 { { 0xf2, 0xc2, 0x95, 0xf2, /* round key */
83 /* Round 3 */
99 { { 0x3d, 0x80, 0x47, 0x7d, /* round key */
128 int i, n = sizeof(rounds) / sizeof(Round);
172 * We must compute a different round key: apply InvMixColumns to
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/qemu/tests/tcg/i386/
H A Dtest-i386-fldcst.c13 /* Round to nearest. */ in main()
22 /* Round downward. */ in main()
31 /* Round toward zero. */ in main()
40 /* Round upward. */ in main()
50 /* Round to nearest. */ in main()
59 /* Round downward. */ in main()
68 /* Round toward zero. */ in main()
77 /* Round upward. */ in main()
87 /* Round to nearest. */ in main()
96 /* Round downward. */ in main()
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H A Dtest-i386-pseudo-denormal.c28 /* Set round-upward. */ in main()
34 printf("FAIL: pseudo-denormal round-to-integer\n"); in main()
H A Dtest-aes.c10 /* aesenclast also adds round key, so supply zero. */ in test_SB_SR()
37 /* aesdeclast also adds round key, so supply zero. */ in test_ISB_ISR()
/qemu/target/arm/tcg/
H A Dvec_internal.h84 bool round, uint32_t *sat) in do_sqrshl_bhs() argument
88 if (round) { in do_sqrshl_bhs()
93 if (round) { in do_sqrshl_bhs()
119 bool round, uint32_t *sat) in do_uqrshl_bhs() argument
121 if (shift <= -(bits + round)) { in do_uqrshl_bhs()
124 if (round) { in do_uqrshl_bhs()
150 bool round, uint32_t *sat) in do_suqrshl_bhs() argument
156 return do_uqrshl_bhs(src, shift, bits, round, sat); in do_suqrshl_bhs()
160 bool round, uint32_t *sat) in do_sqrshl_d() argument
164 if (round) { in do_sqrshl_d()
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H A Dvfp_helper.c351 #define CONV_FTOI(name, ftype, fsz, sign, round) \ argument
358 return float##fsz##_to_##sign##int32##round(x, fpst); \
402 * must always round-to-nearest; the AArch64 ones honour the FPSCR
404 * round-to-nearest so either helper will work.) AArch32 float-to-fix
405 * must round-to-zero.
425 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \ argument
433 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
590 * value to see if it should instead round up. We instead in recip_estimate_incprec()
593 * integer so we can do the "add one and halve" to round it. in recip_estimate_incprec()
659 case float_round_nearest_even: /* Round to Nearest */ in round_to_inf()
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/qemu/tests/tcg/xtensa/
H A Dtest_fp0_conv.S80 test_ftoi round.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V
81 test_ftoi round.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V
84 test_ftoi round.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V
87 test_ftoi round.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V
88 test_ftoi round.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__
89 test_ftoi round.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__
92 test_ftoi round.s, a2, f0, 0xbfa00000, 1, -2, FSR_I /* -1.25 * 2 */
93 test_ftoi round.s, a2, f0, 0xbfc00000, 0, -2, FSR_I /* -1.5 */
94 test_ftoi round.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */
95 test_ftoi round.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */
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/qemu/target/hexagon/
H A Dfma_emu.c107 uint8_t round; member
117 p->round = 0; in accum_init()
126 a.guard = a.round; in accum_norm_left()
127 a.round = a.sticky; in accum_norm_left()
136 a.round | a.guard | int128_nz(a.mant); in accum_norm_right()
137 a.guard = a.round = 0; in accum_norm_right()
144 a.sticky |= a.round | a.guard | (int128_getlo(a.mant) != 0); in accum_norm_right()
146 a.round = (int128_getlo(a.mant) >> 62) & 1; in accum_norm_right()
153 a.sticky |= a.round; in accum_norm_right()
154 a.round = a.guard; in accum_norm_right()
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/qemu/target/riscv/
H A Dinternals.h84 RISCV_FRM_RNE = 0, /* Round to Nearest, ties to Even */
85 RISCV_FRM_RTZ = 1, /* Round towards Zero */
86 RISCV_FRM_RDN = 2, /* Round Down */
87 RISCV_FRM_RUP = 3, /* Round Up */
88 RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
90 RISCV_FRM_ROD = 8, /* Round to Odd */
H A Dvector_helper.c2176 * As fixed point instructions probably have round mode and saturation,
2588 if (vxrm == 0) { /* round-to-nearest-up (add +0.5 LSB) */ in RVVCALL()
2590 } else if (vxrm == 1) { /* round-to-nearest-even */ in RVVCALL()
2597 } else if (vxrm == 3) { /* round-to-odd (OR bits into LSB, aka "jam") */ in RVVCALL()
2600 return 0; /* round-down (truncate) */ in RVVCALL()
2607 uint8_t round = get_round(vxrm, res, 1); in aadd32() local
2609 return (res >> 1) + round; in aadd32()
2616 uint8_t round = get_round(vxrm, res, 1); in aadd64() local
2620 return ((res >> 1) ^ over) + round; in aadd64()
2645 uint8_t round = get_round(vxrm, res, 1); in RVVCALL() local
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/qemu/tests/fp/
H A Dwrap.c.inc167 static fast_type name(type##_t a, uint_fast8_t round, bool exact) \
171 qsf.float_rounding_mode = sf_rounding_to_qemu(round); \
325 static fast_type name(const extFloat80_t *ap, uint_fast8_t round, \
331 qsf.float_rounding_mode = sf_rounding_to_qemu(round); \
357 static fast_type name(const float128_t *ap, uint_fast8_t round, \
363 qsf.float_rounding_mode = sf_rounding_to_qemu(round); \
412 static type##_t name(type##_t a, uint_fast8_t round, bool exact) \
417 qsf.float_rounding_mode = sf_rounding_to_qemu(round); \
427 static void qemu_extF80M_roundToInt(const extFloat80_t *ap, uint_fast8_t round,
434 qsf.float_rounding_mode = sf_rounding_to_qemu(round);
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/qemu/include/libdecnumber/
H A DdecContext.h38 /* round -- must be one of the enumerated rounding modes */
69 DEC_ROUND_CEILING, /* round towards +infinity */
70 DEC_ROUND_UP, /* round away from 0 */
74 DEC_ROUND_DOWN, /* round towards 0 (truncate) */
75 DEC_ROUND_FLOOR, /* round towards -infinity */
76 DEC_ROUND_05UP, /* round for reround */
85 enum rounding round; /* rounding mode */ member
/qemu/bsd-user/freebsd/
H A Dtarget_os_user.h202 int32_t kf_pad0; /* Round to 64 bit alignment. */
227 /* Round to 64 bit alignment. */
250 /* Round to 64 bit alignment. */
266 /* Round to 64 bit alignment. */
275 /* Round to 64 bit alignment. */
285 uint16_t kf_pad1; /* Round to 32 bit alignment. */
/qemu/target/ppc/
H A Dcpu.c221 /* Best approximation (round to nearest) */ in fpscr_set_rounding_mode()
225 /* Smaller magnitude (round toward zero) */ in fpscr_set_rounding_mode()
229 /* Round toward +infinite */ in fpscr_set_rounding_mode()
234 /* Round toward -infinite */ in fpscr_set_rounding_mode()
/qemu/tests/tcg/aarch64/
H A Dtest-aes.c7 /* aese also adds round key, so supply zero. */ in test_SB_SR()
32 /* aesd also adds round key, so supply zero. */ in test_ISB_ISR()
/qemu/crypto/
H A Daes.c34 #include "crypto/aes-round.h"
1408 /* invert the order of the round keys: */ in AES_set_decrypt_key()
1415 /* apply the inverse MixColumn transform to all round keys but the first and the last: */ in AES_set_decrypt_key()
1461 * and add initial round key: in AES_encrypt()
1468 /* round 1: */ in AES_encrypt()
1473 /* round 2: */ in AES_encrypt()
1478 /* round 3: */ in AES_encrypt()
1483 /* round 4: */ in AES_encrypt()
1488 /* round 5: */ in AES_encrypt()
1493 /* round 6: */ in AES_encrypt()
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/qemu/net/
H A Dannounce.c25 (timer->params.rounds - timer->round - 1) * in qemu_announce_timer_step()
86 timer->round = params->rounds; in qemu_announce_timer_reset()
181 if (--timer->round) { in qemu_announce_self_once()
/qemu/target/s390x/tcg/
H A Dfpu_helper.c424 /* round to nearest with ties away from 0 */ in s390_swap_bfp_rounding_mode()
428 /* round to prepare for shorter precision */ in s390_swap_bfp_rounding_mode()
432 /* round to nearest with ties to even */ in s390_swap_bfp_rounding_mode()
436 /* round to zero */ in s390_swap_bfp_rounding_mode()
440 /* round to +inf */ in s390_swap_bfp_rounding_mode()
444 /* round to -inf */ in s390_swap_bfp_rounding_mode()
720 /* round to integer 32-bit */
731 /* round to integer 64-bit */
742 /* round to integer 128-bit */
/qemu/linux-user/arm/nwfpe/
H A Dfpopcode.h133 | 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) |
144 | 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) |
168 | Round to nearest (default) | 0 | 0 |
169 | Round toward plus infinity | 0 | 1 |
170 | Round toward negative infinity | 1 | 0 |
171 | Round toward zero | 1 | 1 |
/qemu/target/hexagon/imported/
H A Dalu.idef466 Q6INSN(A2_roundsat,"Rd32=round(Rss32):sat",ATTRIBS(),
467 "Round & Saturate to 32-bit Signed",
603 "Cross vector add-sub halfwords with shift, round, and saturation",
613 "Cross vector sub-add halfwords with shift, round, and saturation",
1119 Q6INSN(A4_round_ri,"Rd32=round(Rs32,#u5)",ATTRIBS(),"Round", {RdV = fRNDN(RsV,uiV)>>uiV; })
1120 Q6INSN(A4_round_rr,"Rd32=round(Rs32,Rt32)",ATTRIBS(),"Round", {RdV = fRNDN(RsV,fZXTN(5,32,RtV))>>fZ…
1121 Q6INSN(A4_round_ri_sat,"Rd32=round(Rs32,#u5):sat",ATTRIBS(),"Round", {RdV = (fSAT(fRNDN(RsV,uiV)))>…
1122 Q6INSN(A4_round_rr_sat,"Rd32=round(Rs32,Rt32):sat",ATTRIBS(),"Round", {RdV = (fSAT(fRNDN(RsV,fZXTN(…
1125 Q6INSN(A4_cround_ri,"Rd32=cround(Rs32,#u5)",ATTRIBS(),"Convergent Round", {RdV = fCRNDN(RsV,uiV); })
1126 Q6INSN(A4_cround_rr,"Rd32=cround(Rs32,Rt32)",ATTRIBS(),"Convergent Round", {RdV = fCRNDN(RsV,fZXTN(…
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/qemu/tests/tcg/ppc64/
H A Dtest-aes.c15 /* vcipherlast also adds round key, so supply zero. */ in test_SB_SR()
65 /* vcipherlast also adds round key, so supply zero. */ in test_ISB_ISR()
/qemu/include/crypto/
H A Daes-round.h2 * AES round fragments, generic version
21 #include "host/crypto/aes-round.h"
/qemu/host/include/ppc64/host/crypto/
H A Daes-round.h1 #include "host/include/ppc/host/crypto/aes-round.h"
/qemu/host/include/x86_64/host/crypto/
H A Daes-round.h1 #include "host/include/i386/host/crypto/aes-round.h"

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