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/linux-6.8/Documentation/devicetree/bindings/rng/
Dst,stm32-rng.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rng/st,stm32-rng.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 RNG
14 - Lionel Debieve <lionel.debieve@foss.st.com>
19 - st,stm32-rng
20 - st,stm32mp13-rng
31 clock-error-detect:
35 st,rng-lock-conf:
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/linux-6.8/drivers/net/wireless/ath/carl9170/
Dmain.c25 * Copyright (c) 2007-2008 Atheros Communications, Inc.
190 list_for_each_entry_rcu(tid_info, &ar->tx_ampdu_list, list) { in carl9170_ampdu_gc()
191 spin_lock_bh(&ar->tx_ampdu_list_lock); in carl9170_ampdu_gc()
192 if (tid_info->state == CARL9170_TID_STATE_SHUTDOWN) { in carl9170_ampdu_gc()
193 tid_info->state = CARL9170_TID_STATE_KILLED; in carl9170_ampdu_gc()
194 list_del_rcu(&tid_info->list); in carl9170_ampdu_gc()
195 ar->tx_ampdu_list_len--; in carl9170_ampdu_gc()
196 list_add_tail(&tid_info->tmp_list, &tid_gc); in carl9170_ampdu_gc()
198 spin_unlock_bh(&ar->tx_ampdu_list_lock); in carl9170_ampdu_gc()
201 rcu_assign_pointer(ar->tx_ampdu_iter, tid_info); in carl9170_ampdu_gc()
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/linux-6.8/drivers/char/hw_random/
Dstm32-rng.c1 // SPDX-License-Identifier: GPL-2.0-or-later
59 * struct stm32_rng_config - RNG configuration data
61 * @cr: RNG configuration. 0 means default hardware RNG configuration
72 struct hwrng rng; member
83 * Extracts from the STM32 RNG specification when RNG supports CONDRST.
85 * When a noise source (or seed) error occurs, the RNG stops generating
91 * Indeed, when SEIS is set and SECS is cleared it means RNG performed
92 * the reset automatically (auto-reset).
93 * 2. If SECS was set in step 1 (no auto-reset) wait for CONDRST
97 * 3. If SECS was set in step 1 (no auto-reset) wait for SECS to be
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/linux-6.8/drivers/iio/light/
Djsa1212.c1 // SPDX-License-Identifier: GPL-2.0-only
52 /* JSA1212 CONF REG bits */
92 /* JSA1212 ALS RNG REG bits */
118 struct mutex lock; member
134 ret = regmap_update_bits(data->regmap, JSA1212_CONF_REG, in jsa1212_als_enable()
140 data->als_en = !!status; in jsa1212_als_enable()
150 ret = regmap_update_bits(data->regmap, JSA1212_CONF_REG, in jsa1212_pxs_enable()
156 data->pxs_en = !!status; in jsa1212_pxs_enable()
175 ret = regmap_bulk_read(data->regmap, JSA1212_ALS_DT1_REG, &als_data, 2); in jsa1212_read_als_data()
177 dev_err(&data->client->dev, "als data read err\n"); in jsa1212_read_als_data()
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/linux-6.8/drivers/net/wireless/broadcom/b43legacy/
Dmain.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
7 * Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
14 * driver Copyright(c) 2003 - 2004 Intel Corporation.
27 #include <linux/dma-mapping.h>
157 if (!wl || !wl->current_dev) in b43legacy_ratelimit()
159 if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED) in b43legacy_ratelimit()
179 printk(KERN_INFO "b43legacy-%s: %pV", in b43legacyinfo()
180 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); in b43legacyinfo()
198 printk(KERN_ERR "b43legacy-%s ERROR: %pV", in b43legacyerr()
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/linux-6.8/drivers/net/wireless/broadcom/b43/
Dmain.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
8 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
11 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
17 driver Copyright(c) 2003 - 2004 Intel Corporation.
31 #include <linux/dma-mapping.h>
86 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
368 struct ieee80211_bss_conf *conf,
373 if (!wl || !wl->current_dev) in b43_ratelimit()
375 if (b43_status(wl->current_dev) < B43_STAT_STARTED) in b43_ratelimit()
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Db43.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 /* 32-bit DMA */
68 /* 64-bit DMA */
203 #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
209 #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
211 #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
212 #define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
234 #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
235 #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
330 #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
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