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/linux-6.8/arch/riscv/boot/dts/sophgo/
Dsg2042-cpus.dtsi257 compatible = "thead,c920", "riscv";
259 riscv,isa = "rv64imafdc";
260 riscv,isa-base = "rv64i";
261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
272 mmu-type = "riscv,sv39";
275 compatible = "riscv,cpu-intc";
282 compatible = "thead,c920", "riscv";
284 riscv,isa = "rv64imafdc";
285 riscv,isa-base = "rv64i";
286 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
[all …]
Dcv18xx.dtsi19 compatible = "thead,c906", "riscv";
28 mmu-type = "riscv,sv39";
29 riscv,isa = "rv64imafdc";
30 riscv,isa-base = "rv64i";
31 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
35 compatible = "riscv,cpu-intc";
184 riscv,ndev = <101>;
/linux-6.8/Documentation/devicetree/bindings/riscv/
Dextensions.yaml4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
31 const: riscv
34 riscv,isa:
39 https://riscv.org/specifications/
43 Notably, riscv,isa was defined prior to the creation of the
48 insensitive, letters in the riscv,isa string must be all
54 riscv,isa-base:
62 riscv,isa-extensions:
116 encoding") of the riscv-v-spec.
129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
[all …]
Dcpus.yaml4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
52 - const: riscv
58 - const: riscv
59 - const: riscv # Simulator only
69 https://riscv.org/specifications/
72 - riscv,sv32
73 - riscv,sv39
74 - riscv,sv48
75 - riscv,sv57
76 - riscv,none
[all …]
/linux-6.8/drivers/gpu/drm/tegra/
Driscv.c11 #include "riscv.h"
32 static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset) in riscv_writel() argument
34 writel(value, riscv->regs + offset); in riscv_writel()
37 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv) in tegra_drm_riscv_read_descriptors() argument
39 struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc; in tegra_drm_riscv_read_descriptors()
40 struct tegra_drm_riscv_descriptor *os = &riscv->os_desc; in tegra_drm_riscv_read_descriptors()
41 const struct device_node *np = riscv->dev->of_node; in tegra_drm_riscv_read_descriptors()
47 dev_err(riscv->dev, "failed to read " name ": %d\n", err); \ in tegra_drm_riscv_read_descriptors()
62 dev_err(riscv->dev, "descriptors not available\n"); in tegra_drm_riscv_read_descriptors()
69 int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address, in tegra_drm_riscv_boot_bootrom() argument
[all …]
/linux-6.8/arch/riscv/
DMakefile60 riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
61 riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
62 riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
63 riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
64 riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v
70 riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei
74 riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause
78 KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\…
80 KBUILD_AFLAGS += -march=$(riscv-march-y)
97 KBUILD_CFLAGS += $(call cc-option,-mno-riscv-attribute)
[all …]
/linux-6.8/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
32 riscv,isa = "rv64imac";
33 riscv,isa-base = "rv64i";
34 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
39 compatible = "riscv,cpu-intc";
44 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
56 mmu-type = "riscv,sv39";
58 riscv,isa = "rv64imafdc";
59 riscv,isa-base = "rv64i";
60 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
Dfu740-c000.dtsi26 compatible = "sifive,bullet0", "riscv";
33 riscv,isa = "rv64imac";
34 riscv,isa-base = "rv64i";
35 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
40 compatible = "riscv,cpu-intc";
45 compatible = "sifive,bullet0", "riscv";
57 mmu-type = "riscv,sv39";
60 riscv,isa = "rv64imafdc";
61 riscv,isa-base = "rv64i";
62 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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/linux-6.8/Documentation/devicetree/bindings/perf/
Driscv,pmu.yaml4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
31 https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
35 const: riscv,pmu
37 riscv,event-to-mhpmevent:
54 riscv,event-to-mhpmcounters:
68 riscv,raw-event-to-mhpmcounters:
93 riscv,event-to-mhpmevent: [ "riscv,event-to-mhpmcounters" ]
103 compatible = "riscv,pmu";
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
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/linux-6.8/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi19 compatible = "sifive,e51", "sifive,rocket0", "riscv";
25 riscv,isa = "rv64imac";
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
34 compatible = "riscv,cpu-intc";
40 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
52 mmu-type = "riscv,sv39";
54 riscv,isa = "rv64imafdc";
55 riscv,isa-base = "rv64i";
56 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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/linux-6.8/arch/riscv/boot/dts/thead/
Dth1520.dtsi20 compatible = "thead,c910", "riscv";
22 riscv,isa = "rv64imafdc";
23 riscv,isa-base = "rv64i";
24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
34 mmu-type = "riscv,sv39";
37 compatible = "riscv,cpu-intc";
44 compatible = "thead,c910", "riscv";
46 riscv,isa = "rv64imafdc";
47 riscv,isa-base = "rv64i";
48 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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/linux-6.8/arch/riscv/boot/dts/allwinner/
Dsun20i-d1s.dtsi15 compatible = "thead,c906", "riscv";
25 mmu-type = "riscv,sv39";
27 riscv,isa = "rv64imafdc";
28 riscv,isa-base = "rv64i";
29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
34 compatible = "riscv,cpu-intc";
73 riscv,ndev = <175>;
80 compatible = "riscv,pmu";
81 riscv,event-to-mhpmcounters =
92 riscv,event-to-mhpmevent =
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/linux-6.8/arch/riscv/kernel/tests/
DKconfig.debug2 menu "arch/riscv/kernel Testing and Coverage"
8 bool "arch/riscv/kernel runtime Testing"
11 Enable riscv kernel runtime testing.
16 bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TESTS
20 Enable this option to test riscv module linking at boot. This will
35 endmenu # "arch/riscv/kernel runtime Testing"
/linux-6.8/arch/riscv/boot/dts/renesas/
Dr9a07g043f.dtsi21 compatible = "andestech,ax45mp", "riscv";
26 riscv,isa = "rv64imafdc";
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
31 mmu-type = "riscv,sv39";
42 compatible = "riscv,cpu-intc";
57 riscv,ndev = <511>;
/linux-6.8/arch/riscv/kernel/
Dcpu.c53 if (!of_device_is_compatible(node, "riscv")) { in riscv_early_of_processor_hartid()
69 if (of_property_read_string(node, "riscv,isa-base", &isa)) in riscv_early_of_processor_hartid()
82 if (!of_property_present(node, "riscv,isa-extensions")) in riscv_early_of_processor_hartid()
85 if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 || in riscv_early_of_processor_hartid()
86 of_property_match_string(node, "riscv,isa-extensions", "m") < 0 || in riscv_early_of_processor_hartid()
87 of_property_match_string(node, "riscv,isa-extensions", "a") < 0) { in riscv_early_of_processor_hartid()
96 pr_warn("CPU with hartid=%lu is invalid: this kernel does not parse \"riscv,isa\"", in riscv_early_of_processor_hartid()
101 if (of_property_read_string(node, "riscv,isa", &isa)) { in riscv_early_of_processor_hartid()
102 pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n", in riscv_early_of_processor_hartid()
129 if (of_device_is_compatible(node, "riscv")) { in riscv_of_parent_hartid()
[all …]
/linux-6.8/Documentation/devicetree/bindings/cpu/
Didle-states.yaml322 Documentation/devicetree/bindings/riscv/cpus.yaml
325 http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
370 - riscv,idle-state
381 riscv,sbi-suspend-param:
782 compatible = "riscv";
784 riscv,isa = "rv64imafdc";
785 mmu-type = "riscv,sv48";
791 compatible = "riscv,cpu-intc";
798 compatible = "riscv";
800 riscv,isa = "rv64imafdc";
[all …]
/linux-6.8/arch/riscv/boot/dts/starfive/
Djh7100.dtsi21 compatible = "sifive,u74-mc", "riscv";
34 mmu-type = "riscv,sv39";
36 riscv,isa = "rv64imafdc";
37 riscv,isa-base = "rv64i";
38 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
43 compatible = "riscv,cpu-intc";
50 compatible = "sifive,u74-mc", "riscv";
63 mmu-type = "riscv,sv39";
65 riscv,isa = "rv64imafdc";
66 riscv,isa-base = "rv64i";
[all …]
Djh7110.dtsi23 compatible = "sifive,s7", "riscv";
30 riscv,isa = "rv64imac_zba_zbb";
31 riscv,isa-base = "rv64i";
32 riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
37 compatible = "riscv,cpu-intc";
44 compatible = "sifive,u74-mc", "riscv";
57 mmu-type = "riscv,sv39";
59 riscv,isa = "rv64imafdc_zba_zbb";
60 riscv,isa-base = "rv64i";
61 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
[all …]
/linux-6.8/drivers/clocksource/
Dtimer-riscv.c11 #define pr_fmt(fmt) "riscv-timer: " fmt
26 #include <clocksource/timer-riscv.h>
169 pr_err("RISCV timer registration failed [%d]\n", error); in riscv_timer_init_common()
177 "riscv-timer", &riscv_clock_event); in riscv_timer_init_common()
189 "clockevents/riscv/timer:starting", in riscv_timer_init_common()
192 pr_err("cpu hp setup state failed for RISCV timer [%d]\n", in riscv_timer_init_common()
220 child = of_find_compatible_node(NULL, NULL, "riscv,timer"); in riscv_timer_init_dt()
223 "riscv,timer-cannot-wake-cpu"); in riscv_timer_init_dt()
230 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
/linux-6.8/Documentation/devicetree/bindings/timer/
Driscv,timer.yaml4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
20 in Documentation/devicetree/bindings/riscv/cpus.yaml
25 - riscv,timer
31 riscv,timer-cannot-wake-cpu:
46 compatible = "riscv,timer";
/linux-6.8/Documentation/arch/riscv/
Dacpi.rst9 "riscv-isa-release-1239329-2023-05-23" (commit 1239329
10 ) <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-1239329-2023-05-23>`_
/linux-6.8/tools/testing/kunit/qemu_configs/
Driscv.py11 …'Please ensure that qemu-system-riscv is installed, or edit the path in "qemu_configs/riscv.py"\n')
14 QEMU_ARCH = QemuArchParams(linux_arch='riscv',
23 kernel_path='arch/riscv/boot/Image',
/linux-6.8/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/nvidia/arch/nvalloc/common/inc/
DrmRiscvUcode.h34 // Version 4 = for eb riscv boot
52 // Monitor Data offset within RISCV image and size
57 // Monitor Code offset withtin RISCV image and size
63 // Swbrom Code offset within RISCV image and size
68 // Swbrom Data offset within RISCV image and size
/linux-6.8/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml75 - const: riscv,plic0
95 riscv,cpu-intc node, which has a riscv node as parent.
97 riscv,ndev:
115 - riscv,ndev
173 riscv,ndev = <10>;
/linux-6.8/drivers/clk/sunxi-ng/
DKconfig18 depends on MACH_SUN8I || RISCV || COMPILE_TEST
23 depends on MACH_SUN8I || RISCV || COMPILE_TEST
74 depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST
104 depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST

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