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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044-cpus.dtsi16 compatible = "thead,c920", "riscv";
25 mmu-type = "riscv,sv48";
27 riscv,isa = "rv64imafdcbv";
28 riscv,isa-base = "rv64i";
29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
40 riscv,cbom-block-size = <64>;
41 riscv,cbop-block-size = <64>;
42 riscv,cboz-block-size = <64>;
45 compatible = "riscv,cpu-intc";
52 compatible = "thead,c920", "riscv";
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H A Dsg2042-cpus.dtsi257 compatible = "thead,c920", "riscv";
259 riscv,isa = "rv64imafdc";
260 riscv,isa-base = "rv64i";
261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
274 mmu-type = "riscv,sv39";
278 compatible = "riscv,cpu-intc";
285 compatible = "thead,c920", "riscv";
287 riscv,isa = "rv64imafdc";
288 riscv,isa-base = "rv64i";
289 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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/linux/arch/riscv/boot/dts/spacemit/
H A Dk3.dtsi23 compatible = "spacemit,x100", "riscv";
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
44 riscv,cbom-block-size = <64>;
45 riscv,cbop-block-size = <64>;
46 riscv,cboz-block-size = <64>;
54 mmu-type = "riscv,sv39";
57 compatible = "riscv,cpu-intc";
64 compatible = "spacemit,x100", "riscv";
67 riscv,isa-base = "rv64i";
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H A Dk1.dtsi54 compatible = "spacemit,x60", "riscv";
57 …riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_…
58 riscv,isa-base = "rv64i";
59 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
64 riscv,cbom-block-size = <64>;
65 riscv,cbop-block-size = <64>;
66 riscv,cboz-block-size = <64>;
74 mmu-type = "riscv,sv39";
77 compatible = "riscv,cpu-intc";
84 compatible = "spacemit,x60", "riscv";
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/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
28 riscv,isa:
33 https://riscv.org/specifications/
37 Notably, riscv,isa was defined prior to the creation of the
42 insensitive, letters in the riscv,isa string must be all
48 riscv,isa-base:
56 riscv,isa-extensions:
117 encoding") of the riscv-v-spec.
182 request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
188 of riscv-j-extension.
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H A Dcpus.yaml4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
70 - const: riscv
77 - const: riscv
78 - const: riscv # Simulator only
88 https://riscv.org/specifications/
91 - riscv,sv32
92 - riscv,sv39
93 - riscv,sv48
94 - riscv,sv57
95 - riscv,none
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/linux/arch/riscv/
H A DMakefile61 riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
62 riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
63 riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
64 riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
65 riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v
75 riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei
79 riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZACAS) := $(riscv-march-y)_zacas
82 riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZABHA) := $(riscv-march-y)_zabha
84 KBUILD_BASE_ISA = -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1…
91 KBUILD_AFLAGS += -march=$(riscv-march-y)
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,aplic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
16 https://github.com/riscv/riscv-aia.
32 - const: riscv,aplic
47 RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
58 riscv,num-sources:
66 riscv,children:
79 riscv,delegation:
95 riscv,hart-indexes:
104 riscv,delegation: [ "riscv,children" ]
111 - riscv,num-sources
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H A Driscv,imsics.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
52 - const: riscv,imsics
76 to should be a riscv,cpu-intc node, which has a CPU node (i.e. RISC-V
79 riscv,num-ids:
86 riscv,num-guest-ids:
93 riscv,num-ids property.
95 riscv,guest-index-bits:
102 riscv,hart-index-bits:
109 riscv,group-index-bits:
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H A Driscv,rpmi-mpxy-system-msi.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,rpmi-mpxy-system-msi.yaml#
31 https://github.com/riscv-non-isa/riscv-rpmi/releases
34 https://github.com/riscv-non-isa/riscv-sbi-doc/releases
40 const: riscv,rpmi-mpxy-system-msi
47 riscv,sbi-mpxy-channel-id:
56 - riscv,sbi-mpxy-channel-id
63 compatible = "riscv,rpmi-mpxy-system-msi";
65 riscv,sbi-mpxy-channel-id = <0x2000>;
/linux/drivers/gpu/drm/tegra/
H A Driscv.c11 #include "riscv.h"
32 static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset) in riscv_writel() argument
34 writel(value, riscv->regs + offset); in riscv_writel()
37 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv) in tegra_drm_riscv_read_descriptors() argument
39 struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc; in tegra_drm_riscv_read_descriptors()
40 struct tegra_drm_riscv_descriptor *os = &riscv->os_desc; in tegra_drm_riscv_read_descriptors()
41 const struct device_node *np = riscv->dev->of_node; in tegra_drm_riscv_read_descriptors()
47 dev_err(riscv->dev, "failed to read " name ": %d\n", err); \ in tegra_drm_riscv_read_descriptors()
62 dev_err(riscv->dev, "descriptors not available\n"); in tegra_drm_riscv_read_descriptors()
69 int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address, in tegra_drm_riscv_boot_bootrom() argument
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/linux/arch/riscv/boot/dts/tenstorrent/
H A Dblackhole.dtsi16 compatible = "sifive,x280", "sifive,rocket0", "riscv";
19 mmu-type = "riscv,sv57";
20 riscv,isa-base = "rv64i";
21 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
25 compatible = "riscv,cpu-intc";
32 compatible = "sifive,x280", "sifive,rocket0", "riscv";
35 mmu-type = "riscv,sv57";
36 riscv,isa-base = "rv64i";
37 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
41 compatible = "riscv,cpu-intc";
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/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
32 riscv,isa = "rv64imac";
33 riscv,isa-base = "rv64i";
34 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
39 compatible = "riscv,cpu-intc";
44 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
56 mmu-type = "riscv,sv39";
58 riscv,isa = "rv64imafdc";
59 riscv,isa-base = "rv64i";
60 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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H A Dfu740-c000.dtsi26 compatible = "sifive,bullet0", "riscv";
33 riscv,isa = "rv64imac";
34 riscv,isa-base = "rv64i";
35 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
40 compatible = "riscv,cpu-intc";
45 compatible = "sifive,bullet0", "riscv";
57 mmu-type = "riscv,sv39";
60 riscv,isa = "rv64imafdc";
61 riscv,isa-base = "rv64i";
62 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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/linux/arch/riscv/boot/dts/andes/
H A Dqilai.dtsi20 compatible = "andestech,ax45mp", "riscv";
23 riscv,isa-base = "rv64i";
24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
27 mmu-type = "riscv,sv39";
38 compatible = "andestech,cpu-intc", "riscv,cpu-intc";
45 compatible = "andestech,ax45mp", "riscv";
48 riscv,isa-base = "rv64i";
49 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
52 mmu-type = "riscv,sv39";
64 "riscv,cpu-intc";
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/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
31 https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
35 const: riscv,pmu
37 riscv,event-to-mhpmevent:
54 riscv,event-to-mhpmcounters:
68 riscv,raw-event-to-mhpmcounters:
93 riscv,event-to-mhpmevent: [ "riscv,event-to-mhpmcounters" ]
103 compatible = "riscv,pmu";
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
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/linux/Documentation/devicetree/bindings/iommu/
H A Driscv,iommu.yaml4 $id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
22 Visit https://github.com/riscv-non-isa/riscv-iommu for more details.
31 # actually required. For non-PCIe hardware implementations 'riscv,iommu'
37 - qemu,riscv-iommu
38 - const: riscv,iommu
42 - const: riscv,pci-iommu
84 compatible = "qemu,riscv-iommu", "riscv,iommu";
104 compatible = "qemu,riscv-iommu", "riscv,iommu";
114 compatible = "qemu,riscv-iommu", "riscv,iommu";
142 compatible = "pci1efd,edf1", "riscv,pci-iommu";
/linux/Documentation/devicetree/bindings/mailbox/
H A Driscv,rpmi-shmem-mbox.yaml4 $id: http://devicetree.org/schemas/mailbox/riscv,rpmi-shmem-mbox.yaml#
24 https://github.com/riscv-non-isa/riscv-rpmi/releases
28 const: riscv,rpmi-shmem-mbox
59 riscv,slot-size:
65 riscv,a2p-doorbell-value:
71 riscv,p2a-doorbell-sysmsi-index:
87 - riscv,slot-size
102 compatible = "riscv,rpmi-shmem-mbox";
107 riscv,slot-size = <64>;
113 compatible = "riscv,rpmi-shmem-mbox";
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/linux/arch/riscv/boot/dts/eswin/
H A Deic7700.dtsi18 compatible = "sifive,p550", "riscv";
30 mmu-type = "riscv,sv48";
33 riscv,isa-base = "rv64i";
34 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
39 compatible = "riscv,cpu-intc";
46 compatible = "sifive,p550", "riscv";
58 mmu-type = "riscv,sv48";
61 riscv,isa-base = "rv64i";
62 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
67 compatible = "riscv,cpu-intc";
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/linux/arch/riscv/kernel/tests/
H A DKconfig.debug2 menu "arch/riscv/kernel Testing and Coverage"
8 bool "arch/riscv/kernel runtime Testing"
11 Enable riscv kernel runtime testing.
16 bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TESTS
20 Enable this option to test riscv module linking at boot. This will
34 tristate "KUnit test for riscv kprobes" if !KUNIT_ALL_TESTS
39 Enable testing for riscv kprobes. Useful for riscv and/or kprobes
47 endmenu # "arch/riscv/kernel runtime Testing"
/linux/Documentation/devicetree/bindings/clock/
H A Driscv,rpmi-mpxy-clock.yaml4 $id: http://devicetree.org/schemas/clock/riscv,rpmi-mpxy-clock.yaml#
28 https://github.com/riscv-non-isa/riscv-rpmi/releases
31 https://github.com/riscv-non-isa/riscv-sbi-doc/releases
37 const: riscv,rpmi-mpxy-clock
44 riscv,sbi-mpxy-channel-id:
53 - riscv,sbi-mpxy-channel-id
60 compatible = "riscv,rpmi-mpxy-clock";
62 riscv,sbi-mpxy-channel-id = <0x1000>;
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi19 compatible = "sifive,e51", "sifive,rocket0", "riscv";
25 riscv,isa = "rv64imac";
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
34 compatible = "riscv,cpu-intc";
40 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
52 mmu-type = "riscv,sv39";
54 riscv,isa = "rv64imafdc";
55 riscv,isa-base = "rv64i";
56 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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/linux/tools/testing/selftests/riscv/
H A DREADME4 - These tests are riscv specific and so not built or run but just skipped
5 completely when env-variable ARCH is found to be different than 'riscv'.
10 $ make TARGETS=riscv kselftest-clean
11 $ make TARGETS=riscv kselftest
15 $ make -C tools/testing/selftests TARGETS=riscv \
18 or, alternatively, only specific riscv/ subtargets can be picked:
20 $ make -C tools/testing/selftests TARGETS=riscv RISCV_SUBTARGETS="mm vector" \
/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1s.dtsi17 compatible = "thead,c906", "riscv";
27 mmu-type = "riscv,sv39";
29 riscv,isa = "rv64imafdc";
30 riscv,isa-base = "rv64i";
31 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
37 compatible = "riscv,cpu-intc";
76 riscv,ndev = <175>;
83 compatible = "riscv,pmu";
84 riscv,event-to-mhpmcounters =
95 riscv,event-to-mhpmevent =
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/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml322 Documentation/devicetree/bindings/riscv/cpus.yaml
325 http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
370 - riscv,idle-state
381 riscv,sbi-suspend-param:
782 compatible = "riscv";
784 riscv,isa = "rv64imafdc";
785 mmu-type = "riscv,sv48";
791 compatible = "riscv,cpu-intc";
798 compatible = "riscv";
800 riscv,isa = "rv64imafdc";
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