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/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5351.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
24 - silabs,si5351a # Si5351A, 20-QFN package
25 - silabs,si5351a-msop # Si5351A, 10-MSOP package
26 - silabs,si5351b # Si5351B, 20-QFN package
27 - silabs,si5351c # Si5351C, 20-QFN package
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H A Dqcom,qca8k-nsscc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
10 - Bjorn Andersson <andersson@kernel.org>
11 - Luo Jie <quic_luoj@quicinc.com>
18 include/dt-bindings/clock/qcom,qca8k-nsscc.h
19 include/dt-bindings/reset/qcom,qca8k-nsscc.h
24 - const: qcom,qca8084-nsscc
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H A Dqcom,qdu1000-ecpricc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qdu1000-ecpricc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ECPRI Clock & Reset Controller for QDU1000 and QRU1000
10 - Taniya Das <quic_tdas@quicinc.com>
11 - Imran Shaik <quic_imrashai@quicinc.com>
17 See also: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
22 - qcom,qdu1000-ecpricc
29 - description: Board XO source
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H A Dqcom,ipq9574-nsscc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424
10 - Bjorn Andersson <andersson@kernel.org>
11 - Anusha Rao <quic_anusha@quicinc.com>
18 include/dt-bindings/clock/qcom,ipq5424-nsscc.h
19 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
20 include/dt-bindings/reset/qcom,ipq5424-nsscc.h
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H A Dqcom,ipq5018-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ5018
10 - Sricharan Ramabadhran <quic_srichara@quicinc.com>
17 include/dt-bindings/clock/qcom,ipq5018-gcc.h
18 include/dt-bindings/reset/qcom,ipq5018-gcc.h
22 const: qcom,gcc-ipq5018
26 - description: Board XO source
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H A Dqcom,ipq9574-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ9574
10 - Bjorn Andersson <andersson@kernel.org>
11 - Anusha Rao <quic_anusha@quicinc.com>
18 include/dt-bindings/clock/qcom,ipq9574-gcc.h
19 include/dt-bindings/reset/qcom,ipq9574-gcc.h
23 const: qcom,ipq9574-gcc
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H A Dqcom,sdx75-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SDX75
10 - Imran Shaik <quic_imrashai@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
17 See also: include/dt-bindings/clock/qcom,sdx75-gcc.h
21 const: qcom,sdx75-gcc
25 - description: Board XO source
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H A Dqcom,sm8650-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8650-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8650
10 - Bjorn Andersson <andersson@kernel.org>
16 See also: include/dt-bindings/clock/qcom,sm8650-gcc.h
20 const: qcom,sm8650-gcc
24 - description: Board XO source
25 - description: Board Always On XO source
[all …]
H A Dqcom,sm8550-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8550
10 - Bjorn Andersson <andersson@kernel.org>
16 See also: include/dt-bindings/clock/qcom,sm8550-gcc.h
20 const: qcom,sm8550-gcc
24 - description: Board XO source
25 - description: Sleep clock source
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H A Dqcom,qcs8300-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qcs8300-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Global Clock & Reset Controller on QCS8300
10 - Taniya Das <quic_tdas@quicinc.com>
11 - Imran Shaik <quic_imrashai@quicinc.com>
17 See also: include/dt-bindings/clock/qcom,qcs8300-gcc.h
21 const: qcom,qcs8300-gcc
25 - description: Board XO source
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H A Dqcom,milos-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,milos-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on Milos
10 - Luca Weiss <luca.weiss@fairphone.com>
16 See also: include/dt-bindings/clock/qcom,milos-gcc.h
20 const: qcom,milos-gcc
24 - description: Board XO source
25 - description: Sleep clock source
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H A Dqcom,gcc-sm8350.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8350
10 - Vinod Koul <vkoul@kernel.org>
16 See also: include/dt-bindings/clock/qcom,gcc-sm8350.h
20 const: qcom,gcc-sm8350
24 - description: Board XO source
25 - description: Sleep clock source
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H A Dqcom,x1e80100-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on X1E80100
10 - Rajendra Nayak <quic_rjendra@quicinc.com>
16 See also: include/dt-bindings/clock/qcom,x1e80100-gcc.h
21 - items:
22 - const: qcom,x1p42100-gcc
23 - const: qcom,x1e80100-gcc
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/linux/drivers/reset/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 tristate "ASPEED Reset Driver"
30 This enables the reset controller driver for AST2700.
33 bool "AR71xx Reset Driver" if COMPILE_TEST
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/linux/drivers/video/fbdev/via/
H A Dvia_clock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
30 return ((pll.divisor - 2) << 16) in k800_encode_pll()
32 | (pll.multiplier - 2); in k800_encode_pll()
44 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in cle266_set_primary_pll_encoded()
47 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in cle266_set_primary_pll_encoded()
52 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in k800_set_primary_pll_encoded()
56 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in k800_set_primary_pll_encoded()
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/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-sck-kd-g-revA.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021 - 2022, Xilinx, Inc.
6 * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
15 /dts-v1/;
19 compatible = "xlnx,zynqmp-sk-kd240-rev1",
20 "xlnx,zynqmp-sk-kd240-revB",
21 "xlnx,zynqmp-sk-kd240-revA",
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H A Dzynqmp-sck-kr-g-revA.dtso1 // SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
15 /dts-v1/;
19 compatible = "xlnx,zynqmp-sk-kr260-revA",
20 "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
28 clk_27: clock0 { /* u86 - DP */
29 compatible = "fixed-clock";
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H A Dzynqmp-sck-kr-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2021 - 2022, Xilinx, Inc.
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
15 /dts-v1/;
19 compatible = "xlnx,zynqmp-sk-kr260-revB",
20 "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
28 clk_125: clock0 { /* u87 - GEM0/1 */
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/linux/arch/arm/mach-omap1/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0
3 * OMAP1 reset support
13 /* ARM_SYSST bit shifts related to SoC reset sources */
19 /* Standardized reset source bits (across all OMAP SoCs) */
30 * "Global Software Reset Affects Traffic Controller Frequency". in omap1_restart()
41 * omap1_get_reset_sources - return the source of the SoC's last reset
43 * Returns bits that represent the last reset source for the SoC. The
/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra124-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
20 - description: NVIDIA Tegra124
21 const: nvidia,tegra124-xusb
23 - description: NVIDIA Tegra132
25 - const: nvidia,tegra132-xusb
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/linux/Documentation/devicetree/bindings/power/reset/
H A Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controlled reset
10 - Sebastian Reichel <sre@kernel.org>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
21 is configured as an output, and driven active, triggering a level triggered reset condition.
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
[all …]
/linux/Documentation/devicetree/bindings/display/panel/
H A Dvisionox,g2647fb105.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Visionox G2647FB105 6.47" 1080x2340 MIPI-DSI Panel
10 - Alexander Baransky <sanyapilot496@gmail.com>
13 The Visionox G2647FB105 is a 6.47 inch 1080x2340 MIPI-DSI CMD mode OLED panel.
16 - $ref: panel-common.yaml#
25 vdd3p3-supply:
26 description: 3.3V source voltage rail
28 vddio-supply:
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H A Dsamsung,ams639rq08.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung AMS639RQ08 EA8076-based 6.39" 1080x2340 MIPI-DSI Panel
10 - Danila Tikhonov <danila@jiaxyga.com>
11 - Jens Reidel <adrian@travitia.xyz>
14 The Samsung AMS639RQ08 is a 6.39 inch 1080x2340 MIPI-DSI CMD mode AMOLED panel.
17 - $ref: panel-common.yaml#
26 vdd3p3-supply:
27 description: 3.3V source voltage rail
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H A Dsamsung,ams581vf01.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung AMS581VF01 SOFEF01-based 5.81" 1080x2340 MIPI-DSI Panel
10 - Danila Tikhonov <danila@jiaxyga.com>
13 The Samsung AMS581VF01 is a 5.81 inch 1080x2340 MIPI-DSI CMD mode OLED panel.
16 - $ref: panel-common.yaml#
25 vdd3p3-supply:
26 description: 3.3V source voltage rail
28 vddio-supply:
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/linux/arch/sparc/include/asm/
H A Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
24 #define BBC_PSRC 0x08 /* [W] POR Source */
25 #define BBC_XSRC 0x0c /* [B] XIR Source */
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
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