Searched +full:reset +full:- +full:gpio (Results 1 – 25 of 87) sorted by relevance
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4 * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>5 * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>8 * See the COPYING file in the top-level directory.12 #include "libqtest-single.h"84 #define GPIO_ADDR_MASK (~(GPIO_SIZE - 1))94 static uint32_t gpio_readl(unsigned int gpio, unsigned int offset) in gpio_readl() argument96 return readl(gpio + offset); in gpio_readl()99 static void gpio_writel(unsigned int gpio, unsigned int offset, uint32_t value) in gpio_writel() argument101 writel(gpio + offset, value); in gpio_writel()104 static void gpio_set_bit(unsigned int gpio, unsigned int reg, in gpio_set_bit() argument[all …]
10 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>13 * the COPYING file in the top-level directory.23 #include "hw/gpio/nrf51_gpio.h"40 if (now - start > 600) { in uart_wait_for_event()78 QTestState *qts = qtest_init_with_serial("-M microbit", &sock_fd); in test_nrf51_uart()139 QTestState *qts = qtest_init("-M microbit"); in test_microbit_i2c()190 QTestState *qts = qtest_init("-M microbit"); in test_nrf51_nvmc()196 /* Test write-read config register */ in test_nrf51_nvmc()281 QTestState *qts = qtest_init("-M microbit"); in test_nrf51_gpio()283 /* Check reset state */ in test_nrf51_gpio()[all …]
4 * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>5 * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>8 * See the COPYING file in the top-level directory.12 #include "libqtest-single.h"81 * Test that reserved bits stay at reset value in test_reserved_bits()83 * in all reserved bits (keeping reset value for in test_reserved_bits()85 * register is still at reset value in test_reserved_bits()195 * Test that GPIO rising lines result in an irq in test_interrupt()220 /* irq 15 is high at reset because GPIOA15 is high at reset */ in test_interrupt()255 * Test that an irq is generated only by the right GPIO in test_irq_gpio_multiplexer()[all …]
22 * -----------31 * information to the caller and must be re-entrant.57 * ---------------62 * DeviceListener can save the QOpts passed to it for re-using it73 DEV_NVECTORS_UNSPECIFIED = -1,101 * struct DeviceClass - The base class for all devices.107 * @sync_config: Callback function invoked when QMP command device-sync-config136 * ensures a compile-time error if someone attempts to assign137 * dc->props directly.148 * @user_creatable: Can user instantiate with -device / device_add?[all …]
2 * GPIO qemu power controller8 * Virtual gpio driver which can be used on top of pl06110 * case is gpio driver for secure world application (ARM14 * See the COPYING file in the top-level directory.15 * SPDX-License-Identifier: GPL-2.0-or-later20 * two named input GPIO lines:21 * 'reset' : when asserted, trigger system reset29 #define TYPE_GPIOPWR "gpio-pwr"54 qdev_init_gpio_in_named(dev, gpio_pwr_reset, "reset", 1); in gpio_pwr_init()
2 * Nuvoton NPCM7xx General Purpose Input / Output (GPIO)18 #include "hw/gpio/npcm7xx_gpio.h"20 #include "hw/qdev-properties.h"28 /* 32-bit register indices. */70 uint32_t din_new = s->regs[NPCM7XX_GPIO_DIN]; in npcm7xx_gpio_update_events()73 s->regs[NPCM7XX_GPIO_EVST] |= din_new & ~s->regs[NPCM7XX_GPIO_EVTYP]; in npcm7xx_gpio_update_events()75 s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & s->regs[NPCM7XX_GPIO_EVTYP] in npcm7xx_gpio_update_events()76 & s->regs[NPCM7XX_GPIO_EVBE]); in npcm7xx_gpio_update_events()78 s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & din_new in npcm7xx_gpio_update_events()79 & s->regs[NPCM7XX_GPIO_EVTYP]); in npcm7xx_gpio_update_events()[all …]
4 imx_gpio_read(const char *id, const char *reg, uint32_t value) "%s:[%s] -> 0x%" PRIx325 imx_gpio_write(const char *id, const char *reg, uint32_t value) "%s:[%s] <- 0x%" PRIx326 imx_gpio_set(const char *id, int line, int level) "%s:[%d] <- %d"22 pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-15 [%s]"23 …ription, unsigned id, unsigned prev_state, unsigned current_state) "%s GPIO id:%u status: %u -> %u"27 pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"28 pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"32 pl061_reset(const char *id) "%s reset"45 stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s addr: 0x%" PRIx64 " "46 stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s addr: 0x%" PRIx64 " val: 0x%…[all …]
2 * STM32L4x5 GPIO (General Purpose Input/Ouput)4 * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>5 * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>7 * SPDX-License-Identifier: GPL-2.0-or-later10 * See the COPYING file in the top-level directory.15 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.16 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html21 #include "hw/gpio/stm32l4x5_gpio.h"24 #include "hw/qdev-clock.h"25 #include "hw/qdev-properties.h"[all …]
2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK11 * 3) PRCI (Power, Reset, Clock, Interrupt)12 * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM15 * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.33 #include "qemu/error-report.h"83 if (machine->ram_size != mc->default_ram_size) { in sifive_e_machine_init()84 char *sz = size_to_str(mc->default_ram_size); in sifive_e_machine_init()91 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC); in sifive_e_machine_init()92 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); in sifive_e_machine_init()96 memmap[SIFIVE_E_DEV_DTIM].base, machine->ram); in sifive_e_machine_init()[all …]
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu13 * 3) PRCI (Power, Reset, Clock, Interrupt)14 * 4) GPIO (General Purpose Input/Output Controller)15 * 5) OTP (One-Time Programmable) memory with stored serial number39 #include "qemu/error-report.h"99 uint64_t mem_size = ms->ram_size; in create_fdt()111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()114 fdt = ms->fdt = create_device_tree(&s->fdt_size); in create_fdt()122 "sifive,hifive-unleashed-a00"); in create_fdt()[all …]
18 * + QOM property "scc-cfg4": value of the read-only CFG4 register19 * + QOM property "scc-aid": value of the read-only SCC_AID register20 * + QOM property "scc-id": value of the read-only SCC_ID register21 * + QOM property "scc-cfg0": reset value of the CFG0 register22 * + QOM property array "oscclk": reset values of the OSCCLK registers24 * + named GPIO output "remap": this tracks the value of CFG0 register26 * connect this GPIO line to a function performing that mapping.27 * Boards where bit 0 has no special function should leave the GPIO37 #define TYPE_MPS2_SCC "mps2-scc"
4 * Copyright (C) 2020 Philippe Mathieu-Daudé <f4bug@amsat.org>6 * SPDX-License-Identifier: GPL-2.0-or-later12 #include "hw/qdev-core.h"23 * https://www.lumileds.com/products/color-leds/luxeon-rebel-color/48 * Determines whether a GPIO is using a positive (active-high)49 * logic (when used with GPIO, the intensity at reset is related50 * to the GPIO polarity).77 * This utility is meant for LED connected to GPIO.84 * @gpio_polarity: GPIO polarity
4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>7 * SPDX-License-Identifier: GPL-2.0-or-later10 * See the COPYING file in the top-level directory.20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.21 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html30 #include "hw/qdev-clock.h"33 #include "hw/gpio/stm32l4x5_gpio.h"75 s->memrmp = 0x00000000; in stm32l4x5_syscfg_hold_reset()76 s->cfgr1 = 0x7C000001; in stm32l4x5_syscfg_hold_reset()[all …]
2 * STM32L4x5 GPIO (General Purpose Input/Ouput)4 * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>5 * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>7 * SPDX-License-Identifier: GPL-2.0-or-later10 * See the COPYING file in the top-level directory.15 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.16 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html25 #define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"36 /* GPIO registers */48 /* GPIO registers reset values */[all …]
4 * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>5 * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>7 * SPDX-License-Identifier: GPL-2.0-or-later10 * See the COPYING file in the top-level directory.20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.21 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html27 #include "system/address-spaces.h"29 #include "hw/or-irq.h"32 #include "hw/gpio/stm32l4x5_gpio.h"33 #include "hw/qdev-clock.h"[all …]
21 #include "hw/char/serial-mm.h"24 #include "hw/qdev-clock.h"25 #include "hw/qdev-properties.h"30 #include "target/arm/cpu-qom.h"79 * Interrupt lines going into the GIC. This does not include internal Cortex-A9153 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */171 /* Direct memory-mapped access to SPI0 CS0-1. */177 /* Direct memory-mapped access to SPI3 CS0-3. */203 /* Direct memory-mapped access to each SMBus Module. */332 rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup), in npcm7xx_write_board_setup()[all …]
20 #define TYPE_BITBAND "ARM-bitband-memory"40 * + Unnamed GPIO input lines: external IRQ lines for the NVIC41 * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ.42 * If this GPIO is not wired up then the NVIC will default to performing44 * + Property "cpu-type": CPU type to instantiate45 * + Property "num-irq": number of external IRQ lines46 * + Property "num-prio-bits": number of priority bits in the NVIC48 * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal51 * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object)52 * + Property "init-nsvtor": non-secure VTOR reset value (forwarded to CPU object)[all …]
2 * ARM SSE (Subsystems for Embedded): IoTKit, SSE-20014 * hardware, which include the IoT Kit and the SSE-050, SSE-100 and15 * SSE-200. Currently we model:16 * - the Arm IoT Kit which is documented in18 * - the SSE-200 which is documented in22 * a Cortex-M3329 * space are secure and non-secure aliases of each other30 * The SSE-200 additionally contains:31 * a second Cortex-M3337 * per-CPU identity and control register blocks[all …]
... help' without arguments for list of all known commands #gpio-cells alloc space exhausted DRAM: WARNING: adjusting ...
35 #define NPCM7XX_WATCHDOG_RESET_GPIO_OUT "npcm7xx-clk-watchdog-reset-gpio-out"40 * struct NPCM7xxBaseTimer - Basic functionality that both regular timer and53 * struct NPCM7xxTimer - Individual timer state.71 * struct NPCM7xxWatchdogTimer - The watchdog timer state.74 * @reset_signal: The GPIO used to send a reset signal.89 * struct NPCM7xxTimerCtrlState - Timer Module device state.109 #define TYPE_NPCM7XX_TIMER "npcm7xx-timer"
25 #include "hw/m68k/q800-glue.h"29 #include "hw/qdev-properties.h"42 * controlled from the VIA1 auxmode GPIO (port B bit 6) which are documented45 * A/UX mode (Linux, NetBSD, auxmode GPIO low)54 * Level 7: NMIs: parity errors, RESET button, YANCC error56 * Classic mode (default: used by MacOS, A/UX 3.0.1, auxmode GPIO high)65 * Level 7: Non-maskable: parity errors, RESET button76 if (s->auxmode) { in GLUE_set_irq()89 qemu_set_irq(s->irqs[GLUE_IRQ_NUBUS_9], level); in GLUE_set_irq()101 /* Route to VIA2 instead, negative edge-triggered */ in GLUE_set_irq()[all …]
8 ARM1176JZF-S core, 512 MiB of RAM10 Cortex-A7 (4 cores), 1 GiB of RAM12 Cortex-A53 (4 cores), 512 MiB of RAM14 Cortex-A53 (4 cores), 1 GiB of RAM16 Cortex-A72 (4 cores), 2 GiB of RAM19 -------------------21 * ARM1176JZF-S, Cortex-A7, Cortex-A53 or Cortex-A72 CPU24 * Clock and reset controller (CPRMAN)26 * GPIO controller27 * Serial ports (BCM2835 AUX - 16550 based - and PL011)[all …]
1 STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olimex-stm32-h405``, ``stm32vl…4 The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by7 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html9 The STM32F1 series is based on ARM Cortex-M3 core. The following machines are12 - ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcontroller14 The STM32F2 series is based on ARM Cortex-M3 core. The following machines are17 - ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller19 The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L420 ultra-low-power series. The STM32F4 series is pin-to-pin compatible with STM32F2 series.21 The following machines are based on this ARM Cortex-M4F chip :[all …]
1 # core qdev-related obj files, also used by *-user and unit tests4 'qdev-properties.c',8 'vmstate-if.c',9 # irq.c needed for qdev GPIO handling:12 'qdev-clock.c',15 common_ss.add(files('cpu-common.c'))16 common_ss.add(files('machine-smp.c'))17 system_ss.add(when: 'CONFIG_FITLOADER', if_true: files('loader-fit.c'))18 system_ss.add(when: 'CONFIG_GENERIC_LOADER', if_true: files('generic-loader.c'))19 system_ss.add(when: 'CONFIG_GUEST_LOADER', if_true: files('guest-loader.c'))[all …]
13 * This is a model of the "APB watchdog" which is part of the Cortex-M14 * System Design Kit (CMSDK) and documented in the Cortex-M System16 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit23 * In real hardware the watchdog's reset output is just a GPIO line25 * (For instance the IoTKit does this with the non-secure watchdog, so that26 * secure code can control whether non-secure code can perform a system27 * reset via its watchdog.) In QEMU, we just wire up the watchdog reset39 #define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog"44 * cmsdk-apb-watchdog device.46 #define TYPE_LUMINARY_WATCHDOG "luminary-watchdog"