| /linux-6.15/drivers/reset/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
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| D | reset-scmi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ARM System Control and Management Interface (ARM SCMI) reset driver
5 * Copyright (C) 2019-2021 ARM Ltd.
11 #include <linux/reset-controller.h>
17 * struct scmi_reset_data - reset controller information structure
18 * @rcdev: reset controller entity
19 * @ph: ARM SCMI protocol handle used for communication with system controller
27 #define to_scmi_handle(p) (to_scmi_reset_data(p)->ph)
30 * scmi_reset_assert() - assert device reset
31 * @rcdev: reset controller entity
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| /linux-6.15/Documentation/driver-api/ |
| D | reset.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
4 Reset controller API
10 Reset controllers are central units that control the reset signals to multiple
12 The reset controller API is split into two parts:
13 the `consumer driver interface <#consumer-driver-interface>`__ (`API reference
14 <#reset-consumer-api>`__), which allows peripheral drivers to request control
15 over their reset input signals, and the `reset controller driver interface
16 <#reset-controller-driver-interface>`__ (`API reference
17 <#reset-controller-driver-api>`__), which is used by drivers for reset
18 controller devices to register their reset controls to provide them to the
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| /linux-6.15/arch/arm64/boot/dts/apple/ |
| D | s8001-pmgr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
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| D | t8103-pmgr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 ps_sbr: power-controller@100 {
11 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
13 #power-domain-cells = <0>;
14 #reset-cells = <0>;
16 apple,always-on; /* Core device */
19 ps_aic: power-controller@108 {
20 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
22 #power-domain-cells = <0>;
23 #reset-cells = <0>;
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| D | t8011-pmgr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
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| D | t8015-pmgr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
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| D | t8112-pmgr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 ps_sbr: power-controller@100 {
11 compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";
13 #power-domain-cells = <0>;
14 #reset-cells = <0>;
16 apple,always-on; /* Core device */
19 ps_aic: power-controller@108 {
20 compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";
22 #power-domain-cells = <0>;
23 #reset-cells = <0>;
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| D | s5l8960x-pmgr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 ps_cpu0: power-controller@20000 {
10 compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@20008 {
19 compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
[all …]
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| D | t8012-pmgr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
[all …]
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| D | t8010-pmgr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
[all …]
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| D | t7001-pmgr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 ps_cpu0: power-controller@20000 {
10 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@20008 {
19 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
[all …]
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| D | t7000-pmgr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 ps_cpu0: power-controller@20000 {
9 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
11 #power-domain-cells = <0>;
12 #reset-cells = <0>;
14 apple,always-on; /* Core device */
17 ps_cpu1: power-controller@20008 {
18 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
20 #power-domain-cells = <0>;
21 #reset-cells = <0>;
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| D | s800-0-3-pmgr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
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| D | t600x-pmgr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 DIE_NODE(ps_pms_bridge): power-controller@100 {
10 compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 DIE_NODE(ps_aic): power-controller@108 {
19 compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
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| /linux-6.15/include/linux/ |
| D | reset.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 * struct reset_control_bulk_data - Data used for bulk reset control operations.
16 * @id: reset control consumer ID
17 * @rstc: struct reset_control * to store the associated reset control
19 * The reset APIs provide a series of reset_control_bulk_*() API calls as
20 * a convenience to consumers which require multiple reset controls.
34 * enum reset_control_flags - Flags that can be passed to the reset_control_get functions
35 * to determine the type of reset control.
151 return optional ? 0 : -ENOTSUPP; in __device_reset()
160 return optional ? NULL : ERR_PTR(-ENOTSUPP); in __of_reset_control_get()
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| D | reset-controller.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct reset_control_ops - reset controller driver callbacks
12 * @reset: for self-deasserting resets, does all necessary
13 * things to reset the device
14 * @assert: manually assert the reset line, if supported
15 * @deassert: manually deassert the reset line, if supported
16 * @status: return the status of the reset line, if supported
19 int (*reset)(struct reset_controller_dev *rcdev, unsigned long id); member
30 * struct reset_control_lookup - represents a single lookup entry
32 * @list: internal list of all reset lookup entries
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| /linux-6.15/Documentation/devicetree/bindings/reset/ |
| D | amlogic,meson-reset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson SoC Reset Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
17 - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
18 - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
19 - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
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| D | ti-syscon-reset.txt | 1 TI SysCon Reset Controller
4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
6 typically provided by means of memory-mapped I/O registers. These registers are
12 A SysCon Reset Controller node defines a device that uses a syscon node
13 and provides reset management functionality for various hardware modules
16 SysCon Reset Controller Node
18 Each of the reset provider/controller nodes should be a child of a syscon
22 --------------------
23 - compatible : Should be,
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| D | ti,sci-reset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/ti,sci-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI reset controller
10 - Nishanth Menon <nm@ti.com>
13 Some TI SoCs contain a system controller (like the Power Management Micro
14 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
16 between the host processor running an OS and the system controller happens
17 through a protocol called TI System Control Interface (TI-SCI protocol).
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| /linux-6.15/drivers/reset/sti/ |
| D | reset-syscfg.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include <linux/reset-controller.h>
14 * Reset channel description for a system configuration register based
15 * reset controller.
19 * @reset: Regmap field description of the channel's reset bit.
24 struct reg_field reset; member
30 .reset = REG_FIELD(_rr, _rb, _rb), \
35 .reset = REG_FIELD(_rr, _rb, _rb), }
38 * Description of a system configuration register based reset controller.
40 * @wait_for_ack: The controller will wait for reset assert and de-assert to
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| /linux-6.15/drivers/clk/mediatek/ |
| D | reset.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/reset-controller.h>
14 /* Infra global controller reset set register */
22 * enum mtk_reset_version - Version of MediaTek clock reset controller.
25 * @MTK_RST_MAX: Total quantity of version for MediaTek clock reset controller.
34 * struct mtk_clk_rst_desc - Description of MediaTek clock reset.
35 * @version: Reset version which is defined in enum mtk_reset_version.
36 * @rst_bank_ofs: Pointer to an array containing base offsets of the reset register.
37 * @rst_bank_nr: Quantity of reset bank.
40 * @rst_idx_map_nr: Quantity of reset index map.
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| /linux-6.15/Documentation/devicetree/bindings/mfd/ |
| D | canaan,k210-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan Kendryte K210 System Controller
10 - Damien Le Moal <dlemoal@kernel.org>
13 Canaan Inc. Kendryte K210 SoC system controller which provides a
14 register map for controlling the clocks, reset signals and pin power
20 - const: canaan,k210-sysctl
21 - const: syscon
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| D | altera-a10sr.txt | 4 - compatible : "altr,a10sr"
5 - spi-max-frequency : Maximum SPI frequency.
6 - reg : The SPI Chip Select address for the Arria10
8 - interrupts : The interrupt line the device is connected to.
9 - interrupt-controller : Marks the device node as an interrupt controller.
10 - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
13 masks from ../interrupt-controller/interrupts.txt.
15 The A10SR consists of these sub-devices:
18 ------ ----------
19 a10sr_gpio GPIO Controller
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| /linux-6.15/Documentation/devicetree/bindings/pci/ |
| D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC PCIe RP/EP controller
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
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