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/linux-5.10/Documentation/devicetree/bindings/rtc/
Dingenic,rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs Real-Time Clock DT bindings
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: rtc.yaml#
18 - enum:
19 - ingenic,jz4740-rtc
20 - ingenic,jz4760-rtc
21 - items:
[all …]
/linux-5.10/Documentation/devicetree/bindings/pci/
Dintel-gw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
16 const: intel,lgm-pcie
18 - compatible
23 - const: intel,lgm-pcie
24 - const: snps,dw-pcie
29 "#address-cells":
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/linux-5.10/Documentation/devicetree/bindings/sound/
Dti,tas5086.txt1 Texas Instruments TAS5086 6-channel PWM Processor
5 - compatible: Should contain "ti,tas5086".
6 - reg: The i2c address. Should contain <0x1b>.
10 - reset-gpio: A GPIO spec to define which pin is connected to the
11 chip's !RESET pin. If specified, the driver will
12 assert a hardware reset at probe time.
14 - ti,charge-period: This property should contain the time in microseconds
15 that closely matches the external single-ended
16 split-capacitor charge period. The hardware chip
20 When not specified, the hardware default of 1300ms
[all …]
/linux-5.10/drivers/scsi/
Dmesh.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
5 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
11 * Apr. 21 2002 - BenH Rework bus reset code for new error handler
12 * Add delay after initial bus reset
15 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
18 * - handle aborts correctly
19 * - retry arbitration if lost (unless higher levels do this for us)
20 * - power down the chip when no device is detected
76 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
[all …]
Dmesh.h1 /* SPDX-License-Identifier: GPL-2.0 */
53 #define SEQ_ATN 0x20 /* assert ATN signal */
69 #define SEQ_RESETMESH 0x0e /* reset the controller */
103 #define ERR_SCSIRESET 0x20 /* SCSI bus got reset on us */
124 * The units of the sel_timeout register are 10ms.
DNCR5380.c1 // SPDX-License-Identifier: GPL-2.0
4 * to implement 5380 SCSI drivers under Linux with a non-trantor
13 * +1 (303) 666-5836
24 * 1+ (719) 578-3400
25 * 1+ (800) 334-5454
42 * transfer - some PC's will use the I/O bus, 68K's must use
46 * each 5380 in the system - commands that haven't been issued yet,
51 * allowing multiple commands to propagate all the way to a SCSI-II device
57 * When used in a PIO or pseudo-dma mode, the NCR5380 is a braindead
102 * NCR5380_read(register) - read from the specified register
[all …]
/linux-5.10/drivers/rtc/
Drtc-jz4740.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
66 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
76 } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout); in jz4740_rtc_wait_write_ready()
78 return timeout ? 0 : -EIO; in jz4740_rtc_wait_write_ready()
90 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
93 ctrl = readl(rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
94 } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout); in jz4780_rtc_enable_write()
96 return timeout ? 0 : -EIO; in jz4780_rtc_enable_write()
104 if (rtc->type >= ID_JZ4760) in jz4740_rtc_reg_write()
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/linux-5.10/drivers/net/wireless/intersil/orinoco/
Dorinoco_pci.c4 * (i.e. these are not PCMCIA cards in a PCMCIA-to-PCI bridge).
14 * Some of this code is "inspired" by linux-wlan-ng-0.1.10, but nothing
15 * has been copied from it. linux-wlan-ng-0.1.10 is originally :
20 * (C) Copyright David Gibson, IBM Corp. 2002-2003.
59 /* Bitmask to reset the card */
62 /* Magic timeouts for doing the reset.
63 * Those times are straight from wlan-ng, and it is claimed that they
65 #define HERMES_PCI_COR_ONT (250) /* ms */
66 #define HERMES_PCI_COR_OFFT (500) /* ms */
67 #define HERMES_PCI_COR_BUSYT (500) /* ms */
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/linux-5.10/drivers/macintosh/
Dmediabay.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 #define MB_FCR32(bay, r) ((bay)->base + ((r) >> 2))
33 #define MB_FCR8(bay, r) (((volatile u8 __iomem *)((bay)->base)) + (r))
76 * Wait that number of ms between each step in normal polling mode
81 * Consider the media-bay ID value stable if it is the same for
86 /* Wait after powering up the media bay this delay in ms
92 * Hold the media-bay reset signal true for this many ticks
98 * Wait this long after the reset signal is released and before doing
99 * further operations. After this delay, the IDE reset signal is released
105 * Wait this many ticks after an IDE device (e.g. CD-ROM) is inserted
[all …]
/linux-5.10/drivers/phy/ralink/
Dphy-ralink-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <linux/reset.h>
63 writel(val, phy->base + reg); in u2_phy_w32()
68 return readl(phy->base + reg); in u2_phy_r32()
97 regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1, in ralink_usb_phy_power_on()
98 phy->clk, phy->clk); in ralink_usb_phy_power_on()
101 regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1, in ralink_usb_phy_power_on()
105 /* deassert the reset lines */ in ralink_usb_phy_power_on()
106 reset_control_deassert(phy->rsthost); in ralink_usb_phy_power_on()
107 reset_control_deassert(phy->rstdev); in ralink_usb_phy_power_on()
[all …]
/linux-5.10/drivers/pps/clients/
Dpps-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pps-gpio.c -- PPS client driver using GPIO
9 #define PPS_GPIO_NAME "pps-gpio"
19 #include <linux/pps-gpio.h>
34 struct timer_list echo_timer; /* timer to reset echo active state */
56 rising_edge = gpiod_get_value(info->gpio_pin); in pps_gpio_irq_handler()
57 if ((rising_edge && !info->assert_falling_edge) || in pps_gpio_irq_handler()
58 (!rising_edge && info->assert_falling_edge)) in pps_gpio_irq_handler()
59 pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data); in pps_gpio_irq_handler()
60 else if (info->capture_clear && in pps_gpio_irq_handler()
[all …]
/linux-5.10/drivers/watchdog/
Dpnx4008_wdt.c1 // SPDX-License-Identifier: GPL-2.0
12 * 2005-2006 (c) MontaVista Software, Inc.
34 /* WatchDog Timer - Chapter 23 Page 207 */
87 /* stop counter, initiate counter reset */ in pnx4008_wdt_start()
89 /*wait for reset to complete. 100% guarantee event */ in pnx4008_wdt_start()
92 /* internal and external reset, stop after that */ in pnx4008_wdt_start()
98 /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */ in pnx4008_wdt_start()
100 writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); in pnx4008_wdt_start()
121 wdd->timeout = new_timeout; in pnx4008_wdt_set_timeout()
133 * - For details, see the 'reboot' syscall in kernel/reboot.c in pnx4008_restart_handler()
[all …]
/linux-5.10/include/linux/
Drmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2011-2016 Synaptics Incorporated
21 * struct rmi_2d_axis_alignment - target axis alignment
22 * @swap_axes: set to TRUE if desired to swap x- and y-axis
23 * @flip_x: set to TRUE if desired to flip direction on x-axis
24 * @flip_y: set to TRUE if desired to flip direction on y-axis
25 * @clip_x_low - reported X coordinates below this setting will be clipped to
27 * @clip_x_high - reported X coordinates above this setting will be clipped to
29 * @clip_y_low - reported Y coordinates below this setting will be clipped to
31 * @clip_y_high - reported Y coordinates above this setting will be clipped to
[all …]
/linux-5.10/arch/arm64/boot/dts/rockchip/
Drk3399-gru-scarlet.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-scarlet board device tree source
8 #include "rk3399-gru.dtsi"
14 pp1250_s3: pp1250-s3 {
15 compatible = "regulator-fixed";
16 regulator-name = "pp1250_s3";
19 regulator-always-on;
20 regulator-boot-on;
21 regulator-min-microvolt = <1250000>;
22 regulator-max-microvolt = <1250000>;
[all …]
/linux-5.10/drivers/net/ethernet/chelsio/cxgb/
Dpm3393.c7 * PMC/SIERRA (pm3393) MAC-PHY functionality. *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
96 t1_tpi_read(cmac->adapter, OFFSET(reg), data32); in pmread()
102 t1_tpi_write(cmac->adapter, OFFSET(reg), data32); in pmwrite()
106 /* Port reset. */
124 /* PM3393 - Enabling all hardware block interrupts. in pm3393_interrupt_enable()
147 /* PM3393 - Global interrupt enable in pm3393_interrupt_enable()
153 /* TERMINATOR - PL_INTERUPTS_EXT */ in pm3393_interrupt_enable()
154 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
156 writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
[all …]
/linux-5.10/drivers/gpu/drm/bridge/
Dparade-ps8622.c1 // SPDX-License-Identifier: GPL-2.0-only
69 struct i2c_adapter *adap = client->adapter; in ps8622_set()
73 msg.addr = client->addr + page; in ps8622_set()
81 client->addr + page, reg, val, ret); in ps8622_set()
87 struct i2c_client *cl = ps8622->client; in ps8622_send_config()
138 /* [7:5] DCO_FTRNG=+-40% */ in ps8622_send_config()
148 /* Gitune=-37% */ in ps8622_send_config()
168 /* [7:6] Right-bar GPIO output strength is 8mA */ in ps8622_send_config()
180 err = ps8622_set(cl, 0x01, 0x02, 0x80 | ps8622->max_lane_count); in ps8622_send_config()
185 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
[all …]
Dparade-ps8640.c1 // SPDX-License-Identifier: GPL-2.0-only
79 struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1]; in ps8640_bridge_vdo_control()
97 struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL]; in ps8640_bridge_poweron()
101 if (ps_bridge->powered) in ps8640_bridge_poweron()
104 ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), in ps8640_bridge_poweron()
105 ps_bridge->supplies); in ps8640_bridge_poweron()
111 gpiod_set_value(ps_bridge->gpio_powerdown, 0); in ps8640_bridge_poweron()
112 gpiod_set_value(ps_bridge->gpio_reset, 1); in ps8640_bridge_poweron()
114 gpiod_set_value(ps_bridge->gpio_reset, 0); in ps8640_bridge_poweron()
118 * First wait 200ms and then check the MCU ready flag every 20ms in ps8640_bridge_poweron()
[all …]
/linux-5.10/drivers/scsi/csiostor/
Dcsio_mb.c4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
51 * csio_mb_fw_retval - FW return value from a mailbox response.
60 hdr = (struct fw_cmd_hdr *)(mbp->mb); in csio_mb_fw_retval()
62 return FW_CMD_RETVAL_G(ntohl(hdr->lo)); in csio_mb_fw_retval()
66 * csio_mb_hello - FW HELLO command helper
80 struct fw_hello_cmd *cmdp = (struct fw_hello_cmd *)(mbp->mb); in csio_mb_hello()
84 cmdp->op_to_write = htonl(FW_CMD_OP_V(FW_HELLO_CMD) | in csio_mb_hello()
86 cmdp->retval_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); in csio_mb_hello()
[all …]
/linux-5.10/drivers/net/ethernet/intel/ixgb/
Dixgb_hw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2008 Intel Corporation. */
61 /* Workaround for 82597EX reset errata */ in ixgb_mac_reset()
67 /* Delay a few ms just to allow the reset to complete */ in ixgb_mac_reset()
71 /* Make sure the self-clearing global reset bit did self clear */ in ixgb_mac_reset()
72 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST)); in ixgb_mac_reset()
75 if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN) { in ixgb_mac_reset()
86 if (hw->phy_type == ixgb_phy_type_txn17401) in ixgb_mac_reset()
93 * Reset the transmit and receive units; mask and clear all interrupts.
95 * hw - Struct containing variables accessed by shared code
[all …]
/linux-5.10/arch/mips/include/asm/sn/
Dioc3.h1 /* SPDX-License-Identifier: GPL-2.0 */
50 u8 fill0[0x151 - 0x142 - 1];
56 u8 fill1[0x159 - 0x153 - 1];
62 u8 fill2[0x16a - 0x15b - 1];
67 u8 fill3[0x170 - 0x16b - 1];
153 u32 pad1[(0x20000 - 0x00154) / 4];
157 u32 pad2[(0x40000 - 0x20180) / 4];
160 u32 ssram[(0x80000 - 0x40000) / 4];
163 0x80000 - Access to the generic devices selected with DEV0
165 0xA0000 - Access to the generic devices selected with DEV1
[all …]
/linux-5.10/drivers/pci/controller/dwc/
Dpcie-qcom.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
26 #include <linux/reset.h>
31 #include "pcie-designware.h"
190 struct gpio_desc *reset; member
194 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
198 gpiod_set_value_cansleep(pcie->reset, 1); in qcom_ep_reset_assert()
204 /* Ensure that PERST has been asserted for at least 100 ms */ in qcom_ep_reset_deassert()
206 gpiod_set_value_cansleep(pcie->reset, 0); in qcom_ep_reset_deassert()
[all …]
/linux-5.10/drivers/nvmem/
Dlpc18xx_eeprom.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-provider.h>
17 #include <linux/reset.h>
41 /* EEPROM requires 3 ms of erase/program time between each writing */
57 writel(val, eeprom->reg_base + reg); in lpc18xx_eeprom_writel()
63 return readl(eeprom->reg_base + reg); in lpc18xx_eeprom_readl()
87 return -ETIMEDOUT; in lpc18xx_eeprom_busywait_until_prog()
101 if ((reg > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE) || in lpc18xx_eeprom_gather_write()
102 (reg + bytes > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE)) in lpc18xx_eeprom_gather_write()
103 return -EINVAL; in lpc18xx_eeprom_gather_write()
[all …]
/linux-5.10/drivers/remoteproc/
Dqcom_q6v5_mss.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm self-authenticating modem subsystem remoteproc driver
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
13 #include <linux/dma-mapping.h>
26 #include <linux/reset.h>
233 if (rc != -EPROBE_DEFER) in q6v5_regulator_init()
257 dev_err(qproc->dev, in q6v5_regulator_enable()
268 dev_err(qproc->dev, in q6v5_regulator_enable()
276 dev_err(qproc->dev, "Regulator enable failed\n"); in q6v5_regulator_enable()
283 for (; i >= 0; i--) { in q6v5_regulator_enable()
[all …]
/linux-5.10/drivers/net/wireless/ath/ath10k/
Dtargaddrs.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2016 Qualcomm Atheros, Inc.
36 * Pointer to application-defined area, if any.
50 * General-purpose flag bits, similar to SOC_OPTION_* flags.
103 u32 hi_num_bpatch_streams; /* 0x70 -- unused */
124 * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
125 * [31:16]: wakeup timeout in ms
135 * hi_reset_flag is used to do some stuff when target reset.
136 * such as restore app_start after warm reset or
[all …]
/linux-5.10/drivers/gpu/drm/xlnx/
Dzynqmp_dp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
32 #include <linux/reset.h>
242 * struct zynqmp_dp_link_config - Common link config between source and sink
252 * struct zynqmp_dp_mode - Configured mode of DisplayPort
266 * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
278 * struct zynqmp_dp - Xilinx DisplayPort core
285 * @reset: reset controller
[all …]

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