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/linux/Documentation/netlink/specs/
H A Ddpll.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 ---
8 -
16 -
20 -
23 render-max: true
24 -
26 name: lock-status
31 -
37 -
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H A Dnet_shaper.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 ---
3 name: net-shaper
33 @cap-get operation.
36 -
40 render-max: true
42 - name: unspec
44 -
47 -
52 -
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/linux/Documentation/netlink/
H A Dgenetlink-c.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
3 ---
4 $id: http://kernel.org/schemas/netlink/genetlink-c.yaml#
5 $schema: https://json-schema.org/draft-07/schema
12 len-or-define:
14 pattern: ^[0-9A-Za-z_-]+( - 1)?$
16 len-or-limit:
17 # literal int, const name, or limit based on fixed-width type
18 # e.g. u8-min, u16-max, etc.
20 pattern: ^[0-9A-Za-z_-]+$
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H A Dgenetlink-legacy.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
3 ---
4 $id: http://kernel.org/schemas/netlink/genetlink-legacy.yaml#
5 $schema: https://json-schema.org/draft-07/schema
11 pattern: ^[0-9a-z-]+$
15 len-or-define:
17 pattern: ^[0-9A-Za-z_-]+( - 1)?$
19 len-or-limit:
20 # literal int, const name, or limit based on fixed-width type
21 # e.g. u8-min, u16-max, etc.
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H A Dgenetlink.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
3 ---
4 $id: http://kernel.org/schemas/netlink/genetlink-legacy.yaml#
5 $schema: https://json-schema.org/draft-07/schema
11 pattern: ^[0-9a-z-]+$
15 len-or-define:
17 pattern: ^[0-9A-Za-z_-]+( - 1)?$
19 len-or-limit:
20 # literal int, const name, or limit based on fixed-width type
21 # e.g. u8-min, u16-max, etc.
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H A Dnetlink-raw.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
3 ---
4 $id: http://kernel.org/schemas/netlink/netlink-raw.yaml#
5 $schema: https://json-schema.org/draft-07/schema
11 pattern: ^[0-9a-z-]+$
12 name-cap:
14 pattern: ^[0-9a-zA-Z-]+$
18 len-or-define:
20 pattern: ^[0-9A-Za-z_-]+( - 1)?$
27 required: [ name, doc, attribute-sets, operations ]
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/linux/Documentation/userspace-api/netlink/
H A Dc-code-gen.rst1 .. SPDX-License-Identifier: BSD-3-Clause
7 This document describes how Netlink specifications are used to render
9 allowed in older families by the ``genetlink-c`` protocol level,
17 The upper case is used to denote literal values, e.g. ``$family-CMD``
22 and with dashes (``-``) replaced by underscores (``_``).
25 appended (``do`` -> ``do_``).
30 ``c-family-name`` controls the name of the ``#define`` for the family
31 name, default is ``$family-FAMILY-NAME``.
33 ``c-version-name`` controls the name of the ``#define`` for the version
34 of the family, default is ``$family-FAMILY-VERSION``.
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/linux/drivers/gpu/drm/i915/gt/shaders/clear_kernel/
H A Divb.asm1 // SPDX-License-Identifier: MIT
10 * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
11 * 512 bytes of Render Cache.
20 * DW 1.0 - Block Offset to write Render Cache
21 * DW 1.1 [15:0] - Clear Word
22 * DW 1.2 - Delay iterations
23 * DW 1.3 - Enable Instrumentation (only for debug)
24 * DW 1.4 - Rsvd (intended for context ID)
25 * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
26 * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
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H A Dhsw.asm1 // SPDX-License-Identifier: MIT
10 * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
11 * 512 bytes of Render Cache.
20 * DW 1.0 - Block Offset to write Render Cache
21 * DW 1.1 [15:0] - Clear Word
22 * DW 1.2 - Delay iterations
23 * DW 1.3 - Enable Instrumentation (only for debug)
24 * DW 1.4 - Rsvd (intended for context ID)
25 * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
26 * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
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/linux/drivers/gpu/drm/xe/
H A Dxe_tuning.c1 // SPDX-License-Identifier: MIT
38 { XE_RTP_NAME("Tuning: L3 cache - media"),
49 { XE_RTP_NAME("Tuning: Compression Overfetch - media"),
58 { XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3 - media"),
68 { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
79 { XE_RTP_NAME("Tuning: Stateless compression control - media"),
88 { XE_RTP_NAME("Tuning: L3 RW flush all cache - media"),
102 ENGINE_CLASS(RENDER)),
116 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
121 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
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H A Dxe_gt_freq.c1 // SPDX-License-Identifier: MIT
35 * **Read-only** attributes:
37 * - ``act_freq``: The actual resolved frequency decided by PCODE.
38 * - ``cur_freq``: The current one requested by GuC PC to the PCODE.
39 * - ``rpn_freq``: The Render Performance (RP) N level, which is the minimal one.
40 * - ``rpa_freq``: The Render Performance (RP) A level, which is the achievable one.
42 * - ``rpe_freq``: The Render Performance (RP) E level, which is the efficient one.
44 * - ``rp0_freq``: The Render Performance (RP) 0 level, which is the maximum one.
46 * **Read-write** attributes:
48 * - ``min_freq``: Min frequency request.
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/linux/drivers/gpu/drm/v3d/
H A Dv3d_perfmon.c1 // SPDX-License-Identifier: GPL-2.0
13 …{"FEP", "FEP-valid-primitives-no-rendered-pixels", "[FEP] Valid primitives that result in no rende…
14 …{"FEP", "FEP-valid-primitives-rendered-pixels", "[FEP] Valid primitives for all rendered tiles (pr…
15 {"FEP", "FEP-clipped-quads", "[FEP] Early-Z/Near/Far clipped quads"},
16 {"FEP", "FEP-valid-quads", "[FEP] Valid quads"},
17 …{"TLB", "TLB-quads-not-passing-stencil-test", "[TLB] Quads with no pixels passing the stencil test…
18 …{"TLB", "TLB-quads-not-passing-z-and-stencil-test", "[TLB] Quads with no pixels passing the Z and …
19 …{"TLB", "TLB-quads-passing-z-and-stencil-test", "[TLB] Quads with any pixels passing the Z and ste…
20 {"TLB", "TLB-quads-with-zero-coverage", "[TLB] Quads with all pixels having zero coverage"},
21 …{"TLB", "TLB-quads-with-non-zero-coverage", "[TLB] Quads with any pixels having non-zero coverage"…
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/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_fwif_client.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
27 * Minimum PB = Base Pages + (NUM_TE_PIPES-1)*16K + (NUM_VCE_PIPES-1)*64K +
39 * Since the max of NUM_TE_PIPES and NUM_VCE_PIPES is 4, we have a hard limit
40 * of 4GB minus the Minimum PB. For convenience we take the smaller power-of-2
60 /* Indicates whether this render produces visibility results. */
66 /* Disable pixel merging for this render. */
70 /* Disallow compute overlapped with this render. */
153 * Holds the geometry/fragment fence value to allow the fragment partial render command
252 /* Stride IN BYTES for Z-Buffer in case of RTAs. */
254 /* Stride IN BYTES for S-Buffer in case of RTAs. */
H A Dpvr_rogue_fwif_sf.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
47 * - --- ---- ---- ---- ---- ---- ---- ----
48 * 0-11: id number
49 * 12-15: group id number
50 * 16-19: number of parameters
51 * 20-27: unused
52 * 28-30: active: identify SF packet, otherwise regular int32
80 "Kick 3D: FWCtx 0x%08.8x @ %d, RTD 0x%08x. Partial render:%d, CSW resume:%d, prio:%d" },
96 "Restart TA after partial render" },
98 "Resume TA without partial render" },
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/linux/Documentation/driver-api/mtd/
H A Dspi-intel.rst2 Upgrading BIOS using spi-intel
14 The spi-intel driver makes it possible to read and write the SPI serial
16 any of them set, the whole MTD device is made read-only to prevent
18 contents as read-only but it can be changed from kernel command line,
22 might render the machine unbootable and requires special equipment like
25 Below are the steps how to upgrade MinnowBoard MAX BIOS directly from
28 1) Download and extract the latest Minnowboard MAX BIOS SPI image
31 2) Install mtd-utils package [2]. We need this in order to erase the SPI
33 name "mtd-utils".
67 Erasing 4 Kibyte @ 7ff000 -- 100 % complete
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/linux/drivers/gpu/drm/
H A Ddrm_ioctl.c56 * - GET_UNIQUE ioctl, implemented by drm_getunique is wrapped up in libdrm
58 * - The libdrm drmSetBusid function is backed by the SET_UNIQUE ioctl. All
60 * - The internal set_busid kernel functions and driver callbacks are
63 * - Other ioctls and functions involved are named consistently.
76 * side-effect this fills out the unique name in the master structure.
121 mutex_lock(&dev->master_mutex); in drm_getunique()
122 master = file_priv->master; in drm_getunique()
123 if (u->unique_len >= master->unique_len) { in drm_getunique()
124 if (copy_to_user(u->unique, master->unique, master->unique_len)) { in drm_getunique()
125 mutex_unlock(&dev->master_mutex); in drm_getunique()
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/linux/scripts/
H A Dasn1_compiler.c1 // SPDX-License-Identifier: GPL-2.0-or-later
229 [DIRECTIVE_ENCODING_CONTROL] = "ENCODING-CONTROL",
253 _(MAX),
255 [DIRECTIVE_MINUS_INFINITY] = "MINUS-INFINITY",
265 [DIRECTIVE_PLUS_INFINITY] = "PLUS-INFINITY",
270 [DIRECTIVE_RELATIVE_OID] = "RELATIVE-OID",
325 clen = (dlen < token->size) ? dlen : token->size; in directive_compare()
327 //debug("cmp(%s,%s) = ", token->content, dir); in directive_compare()
329 val = memcmp(token->content, dir, clen); in directive_compare()
335 if (dlen == token->size) { in directive_compare()
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/linux/drivers/base/regmap/
H A Dregcache-maple.c1 // SPDX-License-Identifier: GPL-2.0
3 // Register cache access API - maple tree based cache
19 struct maple_tree *mt = map->cache; in regcache_maple_read()
28 return -ENOENT; in regcache_maple_read()
31 *value = entry[reg - mas.index]; in regcache_maple_read()
41 struct maple_tree *mt = map->cache; in regcache_maple_write()
52 entry[reg - mas.index] = val; in regcache_maple_write()
58 mas_set_range(&mas, reg - 1, reg + 1); in regcache_maple_write()
62 lower = mas_find(&mas, reg - 1); in regcache_maple_write()
65 lower_sz = (mas.last - mas.index + 1) * sizeof(unsigned long); in regcache_maple_write()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_fb.c1 // SPDX-License-Identifier: MIT
6 #include <linux/dma-fence.h>
7 #include <linux/dma-resv.h>
26 #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a))
31 * the cache-line pairs. The compression state of the cache-line pair
32 * is specified by 2 bits in the CCS. Each CCS cache-line represents
33 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
34 * cache-line-pairs. CCS is always Y tiled."
62 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
63 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
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/linux/drivers/video/fbdev/core/
H A Dfbcon.h2 * linux/drivers/video/console/fbcon.h -- Low level frame buffer based console driver
22 * This is the interface between the low-level console driver and the
23 * low-level frame buffer device
27 /* Filled in by the low-level console driver */
117 max_len = max(info->var.green.length, info->var.red.length); in mono_col()
118 max_len = max(info->var.blue.length, max_len); in mono_col()
129 *---------------------------------------------
152 * appropriate flags in fb_info->flags. For example,
158 * (hw-accelerated copyarea() and fillrect())
159 * + use hardware-supported panning on a large virtual screen
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/linux/sound/pci/lx6464es/
H A Dlx_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* -*- linux-c -*- *
16 * [ 44k - ( 44.1k + 48k ) / 2 ]
75 #define MAX_STREAM_BUFFER 5 /* max amount of stream buffers. */
80 /* #define MASK_GRANULARITY (2*MICROBLAZE_IBL_MAX-1) */
130 PSTATE_PURGE = 2, /* the ES channels are now off, render pipes do
132 PSTATE_ACQUIRE = 3, /* the ES channels are now on, render pipes do
170 SF_XRUN = 0x20000000, /* the stream is un x-run state. */
281 #define ED_REGISTRY_ERROR (ED_GN | 0x28) /* <- NCX */
282 #define ED_INVALID_SERVICE (ED_GN | 0x29) /* <- NCX */
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/linux/drivers/iio/dac/
H A Dad5421.c1 // SPDX-License-Identifier: GPL-2.0-only
59 * struct ad5421_state - driver instance specific data
128 .channel = -1,
139 st->data[0].d32 = cpu_to_be32((reg << 16) | val); in ad5421_write_unlocked()
141 return spi_write(st->spi, &st->data[0].d8[1], 3); in ad5421_write_unlocked()
150 mutex_lock(&st->lock); in ad5421_write()
152 mutex_unlock(&st->lock); in ad5421_write()
163 .tx_buf = &st->data[0].d8[1], in ad5421_read()
167 .rx_buf = &st->data[1].d8[1], in ad5421_read()
172 mutex_lock(&st->lock); in ad5421_read()
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/linux/drivers/gpu/drm/vc4/
H A Dvc4_validate.c40 * user-submitted CL and writing the validated copy out to the memory
57 /** Return the width in pixels of a 64-byte microtile. */
75 /** Return the height in pixels of a 64-byte microtile. */
93 * size_is_lt() - Returns whether a miplevel of the given size will
110 struct vc4_dev *vc4 = exec->dev; in vc4_use_bo()
114 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) in vc4_use_bo()
117 if (hindex >= exec->bo_count) { in vc4_use_bo()
119 hindex, exec->bo_count); in vc4_use_bo()
122 obj = to_drm_gem_dma_obj(exec->bo[hindex]); in vc4_use_bo()
123 bo = to_vc4_bo(&obj->base); in vc4_use_bo()
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/linux/drivers/gpu/drm/amd/display/modules/freesync/
H A Dfreesync.c2 * Copyright 2016-2023 Advanced Micro Devices, Inc.
36 /* Number of elements in the render times cache array */
38 /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
72 core_freesync->dc = dc; in mod_freesync_create()
73 return &core_freesync->public; in mod_freesync_create()
119 * 10000) * stream->timing.h_total, in calc_duration_in_us_from_v_total()
120 stream->timing.pix_clk_100hz)); in calc_duration_in_us_from_v_total()
127 unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total; in calc_max_hardware_v_total()
129 if (stream->ctx->dc->caps.vtotal_limited_by_fp2) { in calc_max_hardware_v_total()
130 max_hw_v_total -= stream->timing.v_front_porch + 1; in calc_max_hardware_v_total()
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_regs.h1 /* SPDX-License-Identifier: MIT */
16 * lists of registers (where they're mixed in with other non-MCR registers)
18 * as non-multicast so we can place them on the same list, but we may want
87 * On GEN4, only the render ring INSTDONE exists and has a different
107 /* GM45+ chicken bits -- debug workaround bits that may be required
112 /* Disables pipelining of read flushes past the SF-WIZ interface.
113 * Required on all Ironlake steppings according to the B-Spec, but the
209 * - Power context is saved elsewhere (LLC or stolen)
210 * - Ring/execlist context is saved on SNB, not on IVB
211 * - Extended context size already includes render context size
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