/linux-6.6/drivers/gpu/drm/ci/ |
D | testlist.txt | 1 core_auth@getclient-simple 2 core_auth@getclient-master-drop 3 core_auth@basic-auth 4 core_auth@many-magics 9 drm_read@invalid-buffer 10 drm_read@fault-buffer 11 drm_read@empty-block 12 drm_read@empty-nonblock 13 drm_read@short-buffer-block 14 drm_read@short-buffer-nonblock [all …]
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/linux-6.6/Documentation/userspace-api/netlink/ |
D | c-code-gen.rst | 1 .. SPDX-License-Identifier: BSD-3-Clause 7 This document describes how Netlink specifications are used to render 9 allowed in older families by the ``genetlink-c`` protocol level, 17 The upper case is used to denote literal values, e.g. ``$family-CMD`` 22 and with dashes (``-``) replaced by underscores (``_``). 25 appended (``do`` -> ``do_``). 30 ``c-family-name`` controls the name of the ``#define`` for the family 31 name, default is ``$family-FAMILY-NAME``. 33 ``c-version-name`` controls the name of the ``#define`` for the version 34 of the family, default is ``$family-FAMILY-VERSION``. [all …]
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/linux-6.6/drivers/gpu/drm/i915/gt/ |
D | intel_gt_pm_debugfs.c | 1 // SPDX-License-Identifier: MIT 29 atomic_inc(>->user_wakeref); in intel_gt_pm_debugfs_forcewake_user_open() 31 if (GRAPHICS_VER(gt->i915) >= 6) in intel_gt_pm_debugfs_forcewake_user_open() 32 intel_uncore_forcewake_user_get(gt->uncore); in intel_gt_pm_debugfs_forcewake_user_open() 37 if (GRAPHICS_VER(gt->i915) >= 6) in intel_gt_pm_debugfs_forcewake_user_release() 38 intel_uncore_forcewake_user_put(gt->uncore); in intel_gt_pm_debugfs_forcewake_user_release() 40 atomic_dec(>->user_wakeref); in intel_gt_pm_debugfs_forcewake_user_release() 45 struct intel_gt *gt = inode->i_private; in forcewake_user_open() 54 struct intel_gt *gt = inode->i_private; in forcewake_user_release() 69 struct intel_gt *gt = m->private; in fw_domains_show() [all …]
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D | intel_rps.c | 1 // SPDX-License-Identifier: MIT 43 return rps_to_gt(rps)->i915; in rps_to_i915() 48 return rps_to_gt(rps)->uncore; in rps_to_uncore() 55 return >->uc.guc.slpc; in rps_to_slpc() 62 return intel_uc_uses_guc_slpc(>->uc); in rps_uses_slpc() 67 return mask & ~rps->pm_intrmsk_mbz; in rps_pm_sanitize_mask() 90 last = engine->stats.rps; in rps_timer() 91 engine->stats.rps = dt; in rps_timer() 99 last = rps->pm_timestamp; in rps_timer() 100 rps->pm_timestamp = timestamp; in rps_timer() [all …]
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D | intel_gt_regs.h | 1 /* SPDX-License-Identifier: MIT */ 16 * lists of registers (where they're mixed in with other non-MCR registers) 18 * as non-multicast so we can place them on the same list, but we may want 90 * On GEN4, only the render ring INSTDONE exists and has a different 110 /* GM45+ chicken bits -- debug workaround bits that may be required 115 /* Disables pipelining of read flushes past the SF-WIZ interface. 116 * Required on all Ironlake steppings according to the B-Spec, but the 210 * - Power context is saved elsewhere (LLC or stolen) 211 * - Ring/execlist context is saved on SNB, not on IVB 212 * - Extended context size already includes render context size [all …]
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/linux-6.6/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ |
D | ivb.asm | 1 // SPDX-License-Identifier: MIT 10 * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears 11 * 512 bytes of Render Cache. 20 * DW 1.0 - Block Offset to write Render Cache 21 * DW 1.1 [15:0] - Clear Word 22 * DW 1.2 - Delay iterations 23 * DW 1.3 - Enable Instrumentation (only for debug) 24 * DW 1.4 - Rsvd (intended for context ID) 25 * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount 26 * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count) [all …]
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D | hsw.asm | 1 // SPDX-License-Identifier: MIT 10 * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears 11 * 512 bytes of Render Cache. 20 * DW 1.0 - Block Offset to write Render Cache 21 * DW 1.1 [15:0] - Clear Word 22 * DW 1.2 - Delay iterations 23 * DW 1.3 - Enable Instrumentation (only for debug) 24 * DW 1.4 - Rsvd (intended for context ID) 25 * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount 26 * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count) [all …]
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/linux-6.6/Documentation/netlink/ |
D | genetlink.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 3 --- 4 $id: http://kernel.org/schemas/netlink/genetlink-legacy.yaml# 5 $schema: https://json-schema.org/draft-07/schema 12 len-or-define: 14 pattern: ^[0-9A-Za-z_]+( - 1)?$ 21 required: [ name, doc, attribute-sets, operations ] 36 uapi-header: 37 description: Path to the uAPI header, default is linux/${family-name}.h 51 description: For C-compatible languages, header which already defines this value. [all …]
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D | genetlink-c.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 3 --- 4 $id: http://kernel.org/schemas/netlink/genetlink-c.yaml# 5 $schema: https://json-schema.org/draft-07/schema 12 len-or-define: 14 pattern: ^[0-9A-Za-z_]+( - 1)?$ 21 required: [ name, doc, attribute-sets, operations ] 35 enum: [ genetlink, genetlink-c ] 36 uapi-header: 37 description: Path to the uAPI header, default is linux/${family-name}.h [all …]
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D | genetlink-legacy.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 3 --- 4 $id: http://kernel.org/schemas/netlink/genetlink-legacy.yaml# 5 $schema: https://json-schema.org/draft-07/schema 12 len-or-define: 14 pattern: ^[0-9A-Za-z_]+( - 1)?$ 21 required: [ name, doc, attribute-sets, operations ] 35 enum: [ genetlink, genetlink-c, genetlink-legacy ] # Trim 36 uapi-header: 37 description: Path to the uAPI header, default is linux/${family-name}.h [all …]
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D | netlink-raw.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 3 --- 4 $id: http://kernel.org/schemas/netlink/netlink-raw.yaml# 5 $schema: https://json-schema.org/draft-07/schema 12 len-or-define: 14 pattern: ^[0-9A-Za-z_]+( - 1)?$ 21 required: [ name, doc, attribute-sets, operations ] 31 enum: [ netlink-raw ] # Trim 32 # Start netlink-raw 34 description: Protocol number to use for netlink-raw [all …]
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/linux-6.6/Documentation/netlink/specs/ |
D | netdev.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 9 - 11 name: xdp-act 12 render-max: true 14 - 19 - 23 - 24 name: ndo-xmit 27 - 28 name: xsk-zerocopy [all …]
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/linux-6.6/drivers/gpu/drm/ci/xfails/ |
D | i915-cml-flakes.txt | 1 kms_bw@linear-tiling-2-displays-1920x1080p 2 kms_bw@linear-tiling-2-displays-2560x1440p 3 kms_bw@linear-tiling-2-displays-3840x2160p 4 kms_bw@linear-tiling-3-displays-1920x1080p 5 kms_bw@linear-tiling-3-displays-2560x1440p 6 kms_bw@linear-tiling-3-displays-3840x2160p 7 kms_bw@linear-tiling-4-displays-1920x1080p 8 kms_bw@linear-tiling-4-displays-2560x1440p 9 kms_bw@linear-tiling-4-displays-3840x2160p 10 kms_draw_crc@draw-method-xrgb8888-render-xtiled [all …]
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/linux-6.6/Documentation/driver-api/mtd/ |
D | spi-intel.rst | 2 Upgrading BIOS using spi-intel 14 The spi-intel driver makes it possible to read and write the SPI serial 16 any of them set, the whole MTD device is made read-only to prevent 18 contents as read-only but it can be changed from kernel command line, 22 might render the machine unbootable and requires special equipment like 25 Below are the steps how to upgrade MinnowBoard MAX BIOS directly from 28 1) Download and extract the latest Minnowboard MAX BIOS SPI image 31 2) Install mtd-utils package [2]. We need this in order to erase the SPI 33 name "mtd-utils". 67 Erasing 4 Kibyte @ 7ff000 -- 100 % complete [all …]
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/linux-6.6/drivers/gpu/drm/ |
D | drm_ioctl.c | 57 * - GET_UNIQUE ioctl, implemented by drm_getunique is wrapped up in libdrm 59 * - The libdrm drmSetBusid function is backed by the SET_UNIQUE ioctl. All 61 * - The internal set_busid kernel functions and driver callbacks are 64 * - Other ioctls and functions involved are named consistently. 77 * side-effect this fills out the unique name in the master structure. 122 mutex_lock(&dev->master_mutex); in drm_getunique() 123 master = file_priv->master; in drm_getunique() 124 if (u->unique_len >= master->unique_len) { in drm_getunique() 125 if (copy_to_user(u->unique, master->unique, master->unique_len)) { in drm_getunique() 126 mutex_unlock(&dev->master_mutex); in drm_getunique() [all …]
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/linux-6.6/scripts/ |
D | asn1_compiler.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 229 [DIRECTIVE_ENCODING_CONTROL] = "ENCODING-CONTROL", 253 _(MAX), 255 [DIRECTIVE_MINUS_INFINITY] = "MINUS-INFINITY", 265 [DIRECTIVE_PLUS_INFINITY] = "PLUS-INFINITY", 270 [DIRECTIVE_RELATIVE_OID] = "RELATIVE-OID", 325 clen = (dlen < token->size) ? dlen : token->size; in directive_compare() 327 //debug("cmp(%s,%s) = ", token->content, dir); in directive_compare() 329 val = memcmp(token->content, dir, clen); in directive_compare() 335 if (dlen == token->size) { in directive_compare() [all …]
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/linux-6.6/drivers/base/regmap/ |
D | regcache-maple.c | 1 // SPDX-License-Identifier: GPL-2.0 3 // Register cache access API - maple tree based cache 19 struct maple_tree *mt = map->cache; in regcache_maple_read() 28 return -ENOENT; in regcache_maple_read() 31 *value = entry[reg - mas.index]; in regcache_maple_read() 41 struct maple_tree *mt = map->cache; in regcache_maple_write() 52 entry[reg - mas.index] = val; in regcache_maple_write() 58 mas_set_range(&mas, reg - 1, reg + 1); in regcache_maple_write() 62 lower = mas_find(&mas, reg - 1); in regcache_maple_write() 65 lower_sz = (mas.last - mas.index + 1) * sizeof(unsigned long); in regcache_maple_write() [all …]
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/linux-6.6/drivers/gpu/drm/vc4/ |
D | vc4_validate.c | 40 * user-submitted CL and writing the validated copy out to the memory 55 /** Return the width in pixels of a 64-byte microtile. */ 73 /** Return the height in pixels of a 64-byte microtile. */ 91 * size_is_lt() - Returns whether a miplevel of the given size will 108 struct vc4_dev *vc4 = exec->dev; in vc4_use_bo() 112 if (WARN_ON_ONCE(vc4->is_vc5)) in vc4_use_bo() 115 if (hindex >= exec->bo_count) { in vc4_use_bo() 117 hindex, exec->bo_count); in vc4_use_bo() 120 obj = to_drm_gem_dma_obj(exec->bo[hindex]); in vc4_use_bo() 121 bo = to_vc4_bo(&obj->base); in vc4_use_bo() [all …]
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/linux-6.6/sound/pci/lx6464es/ |
D | lx_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* -*- linux-c -*- * 16 * [ 44k - ( 44.1k + 48k ) / 2 ] 75 #define MAX_STREAM_BUFFER 5 /* max amount of stream buffers. */ 80 /* #define MASK_GRANULARITY (2*MICROBLAZE_IBL_MAX-1) */ 130 PSTATE_PURGE = 2, /* the ES channels are now off, render pipes do 132 PSTATE_ACQUIRE = 3, /* the ES channels are now on, render pipes do 170 SF_XRUN = 0x20000000, /* the stream is un x-run state. */ 281 #define ED_REGISTRY_ERROR (ED_GN | 0x28) /* <- NCX */ 282 #define ED_INVALID_SERVICE (ED_GN | 0x29) /* <- NCX */ [all …]
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/linux-6.6/drivers/gpu/drm/i915/display/ |
D | intel_fb.c | 1 // SPDX-License-Identifier: MIT 16 #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a)) 21 * the cache-line pairs. The compression state of the cache-line pair 22 * is specified by 2 bits in the CCS. Each CCS cache-line represents 23 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled 24 * cache-line-pairs. CCS is always Y tiled." 44 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the 45 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles 46 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of 132 #define DISPLAY_VER_ALL { 0, -1 } [all …]
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/linux-6.6/drivers/gpu/drm/amd/display/modules/freesync/ |
D | freesync.c | 2 * Copyright 2016-2023 Advanced Micro Devices, Inc. 36 /* Number of elements in the render times cache array */ 38 /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */ 71 core_freesync->dc = dc; in mod_freesync_create() 72 return &core_freesync->public; in mod_freesync_create() 117 * 10000) * stream->timing.h_total, in calc_duration_in_us_from_v_total() 118 stream->timing.pix_clk_100hz)); in calc_duration_in_us_from_v_total() 135 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), in mod_freesync_calc_v_total_from_refresh() 136 stream->timing.h_total), 1000000); in mod_freesync_calc_v_total_from_refresh() 139 if (v_total < stream->timing.v_total) { in mod_freesync_calc_v_total_from_refresh() [all …]
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/linux-6.6/drivers/video/fbdev/core/ |
D | fbcon.h | 2 * linux/drivers/video/console/fbcon.h -- Low level frame buffer based console driver 22 * This is the interface between the low-level console driver and the 23 * low-level frame buffer device 27 /* Filled in by the low-level console driver */ 114 max_len = max(info->var.green.length, info->var.red.length); in mono_col() 115 max_len = max(info->var.blue.length, max_len); in mono_col() 130 if (vc->vc_can_do_color) in attr_col_ec() 131 return is_fg ? attr_fgcol(shift,vc->vc_video_erase_char) in attr_col_ec() 132 : attr_bgcol(shift,vc->vc_video_erase_char); in attr_col_ec() 138 is_mono01 = info->fix.visual == FB_VISUAL_MONO01; in attr_col_ec() [all …]
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/linux-6.6/drivers/iio/dac/ |
D | ad5421.c | 1 // SPDX-License-Identifier: GPL-2.0-only 59 * struct ad5421_state - driver instance specific data 128 .channel = -1, 139 st->data[0].d32 = cpu_to_be32((reg << 16) | val); in ad5421_write_unlocked() 141 return spi_write(st->spi, &st->data[0].d8[1], 3); in ad5421_write_unlocked() 150 mutex_lock(&st->lock); in ad5421_write() 152 mutex_unlock(&st->lock); in ad5421_write() 163 .tx_buf = &st->data[0].d8[1], in ad5421_read() 167 .rx_buf = &st->data[1].d8[1], in ad5421_read() 172 mutex_lock(&st->lock); in ad5421_read() [all …]
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/linux-6.6/include/uapi/drm/ |
D | amdgpu_drm.h | 1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 257 #define AMDGPU_CTX_PRIORITY_UNSET -2048 258 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 259 #define AMDGPU_CTX_PRIORITY_LOW -512 368 /* SI-CI-VI: */ 452 /** BO status: 0 - BO is idle, 1 - BO is busy */ 478 /** CS status: 0 - CS completed, 1 - CS still busy */ 545 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ [all …]
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/linux-6.6/drivers/gpu/drm/i915/gem/ |
D | i915_gem_context.c | 2 * SPDX-License-Identifier: MIT 4 * Copyright © 2011-2012 Intel Corporation 13 * supports contexts for the render ring. 19 * would happen if a client ran and piggy-backed off another clients GPU state. 27 * store GPU state, and thus allow GPU clients to not re-emit state (and 31 * The context life cycle is semi-complicated in that context BOs may live 44 * S0->S1: client creates a context 45 * S1->S2: client submits execbuf with context 46 * S2->S3: other clients submits execbuf with context 47 * S3->S1: context object was retired [all …]
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