| /qemu/target/i386/tcg/ |
| H A D | ops_sse_header.h.inc | 20 #define Reg MMXReg
23 #define Reg ZMMReg
34 #define dh_ctype_Reg Reg *
41 DEF_HELPER_4(glue(psrlw, SUFFIX), void, env, Reg, Reg, Reg)
42 DEF_HELPER_4(glue(psraw, SUFFIX), void, env, Reg, Reg, Reg)
43 DEF_HELPER_4(glue(psllw, SUFFIX), void, env, Reg, Reg, Reg)
44 DEF_HELPER_4(glue(psrld, SUFFIX), void, env, Reg, Reg, Reg)
45 DEF_HELPER_4(glue(psrad, SUFFIX), void, env, Reg, Reg, Reg)
46 DEF_HELPER_4(glue(pslld, SUFFIX), void, env, Reg, Reg, Reg)
47 DEF_HELPER_4(glue(psrlq, SUFFIX), void, env, Reg, Reg, Reg)
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| /qemu/gdb-xml/ |
| H A D | microblaze-core.xml | 10 <reg name="r0" bitsize="32" regnum="0"/>
11 <reg name="r1" bitsize="32" type="data_ptr"/>
12 <reg name="r2" bitsize="32"/>
13 <reg name="r3" bitsize="32"/>
14 <reg name="r4" bitsize="32"/>
15 <reg name="r5" bitsize="32"/>
16 <reg name="r6" bitsize="32"/>
17 <reg name="r7" bitsize="32"/>
18 <reg name="r8" bitsize="32"/>
19 <reg name="r9" bitsize="32"/>
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| H A D | power64-core.xml | 10 <reg name="r0" bitsize="64" type="uint64"/>
11 <reg name="r1" bitsize="64" type="uint64"/>
12 <reg name="r2" bitsize="64" type="uint64"/>
13 <reg name="r3" bitsize="64" type="uint64"/>
14 <reg name="r4" bitsize="64" type="uint64"/>
15 <reg name="r5" bitsize="64" type="uint64"/>
16 <reg name="r6" bitsize="64" type="uint64"/>
17 <reg name="r7" bitsize="64" type="uint64"/>
18 <reg name="r8" bitsize="64" type="uint64"/>
19 <reg name="r9" bitsize="64" type="uint64"/>
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| H A D | power-core.xml | 10 <reg name="r0" bitsize="32" type="uint32"/>
11 <reg name="r1" bitsize="32" type="uint32"/>
12 <reg name="r2" bitsize="32" type="uint32"/>
13 <reg name="r3" bitsize="32" type="uint32"/>
14 <reg name="r4" bitsize="32" type="uint32"/>
15 <reg name="r5" bitsize="32" type="uint32"/>
16 <reg name="r6" bitsize="32" type="uint32"/>
17 <reg name="r7" bitsize="32" type="uint32"/>
18 <reg name="r8" bitsize="32" type="uint32"/>
19 <reg name="r9" bitsize="32" type="uint32"/>
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| H A D | power-spe.xml | 10 <reg name="ev0h" bitsize="32" regnum="71"/>
11 <reg name="ev1h" bitsize="32"/>
12 <reg name="ev2h" bitsize="32"/>
13 <reg name="ev3h" bitsize="32"/>
14 <reg name="ev4h" bitsize="32"/>
15 <reg name="ev5h" bitsize="32"/>
16 <reg name="ev6h" bitsize="32"/>
17 <reg name="ev7h" bitsize="32"/>
18 <reg name="ev8h" bitsize="32"/>
19 <reg name="ev9h" bitsize="32"/>
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| H A D | arm-neon.xml | 35 <reg name="d0" bitsize="64" type="neon_d"/>
36 <reg name="d1" bitsize="64" type="neon_d"/>
37 <reg name="d2" bitsize="64" type="neon_d"/>
38 <reg name="d3" bitsize="64" type="neon_d"/>
39 <reg name="d4" bitsize="64" type="neon_d"/>
40 <reg name="d5" bitsize="64" type="neon_d"/>
41 <reg name="d6" bitsize="64" type="neon_d"/>
42 <reg name="d7" bitsize="64" type="neon_d"/>
43 <reg name="d8" bitsize="64" type="neon_d"/>
44 <reg name="d9" bitsize="64" type="neon_d"/>
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| H A D | loongarch-fpu.xml | 16 <reg name="f0" bitsize="64" type="fputype" group="float"/>
17 <reg name="f1" bitsize="64" type="fputype" group="float"/>
18 <reg name="f2" bitsize="64" type="fputype" group="float"/>
19 <reg name="f3" bitsize="64" type="fputype" group="float"/>
20 <reg name="f4" bitsize="64" type="fputype" group="float"/>
21 <reg name="f5" bitsize="64" type="fputype" group="float"/>
22 <reg name="f6" bitsize="64" type="fputype" group="float"/>
23 <reg name="f7" bitsize="64" type="fputype" group="float"/>
24 <reg name="f8" bitsize="64" type="fputype" group="float"/>
25 <reg name="f9" bitsize="64" type="fputype" group="float"/>
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| H A D | avr-cpu.xml | 14 <reg name="r0" bitsize="8" type="int" regnum="0"/>
15 <reg name="r1" bitsize="8" type="int"/>
16 <reg name="r2" bitsize="8" type="int"/>
17 <reg name="r3" bitsize="8" type="int"/>
18 <reg name="r4" bitsize="8" type="int"/>
19 <reg name="r5" bitsize="8" type="int"/>
20 <reg name="r6" bitsize="8" type="int"/>
21 <reg name="r7" bitsize="8" type="int"/>
22 <reg name="r8" bitsize="8" type="int"/>
23 <reg name="r9" bitsize="8" type="int"/>
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| H A D | riscv-64bit-cpu.xml | 10 <reg name="zero" bitsize="64" type="int"/>
11 <reg name="ra" bitsize="64" type="code_ptr"/>
12 <reg name="sp" bitsize="64" type="data_ptr"/>
13 <reg name="gp" bitsize="64" type="data_ptr"/>
14 <reg name="tp" bitsize="64" type="data_ptr"/>
15 <reg name="t0" bitsize="64" type="int"/>
16 <reg name="t1" bitsize="64" type="int"/>
17 <reg name="t2" bitsize="64" type="int"/>
18 <reg name="fp" bitsize="64" type="data_ptr"/>
19 <reg name="s1" bitsize="64" type="int"/>
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| H A D | riscv-32bit-cpu.xml | 10 <reg name="zero" bitsize="32" type="int"/>
11 <reg name="ra" bitsize="32" type="code_ptr"/>
12 <reg name="sp" bitsize="32" type="data_ptr"/>
13 <reg name="gp" bitsize="32" type="data_ptr"/>
14 <reg name="tp" bitsize="32" type="data_ptr"/>
15 <reg name="t0" bitsize="32" type="int"/>
16 <reg name="t1" bitsize="32" type="int"/>
17 <reg name="t2" bitsize="32" type="int"/>
18 <reg name="fp" bitsize="32" type="data_ptr"/>
19 <reg name="s1" bitsize="32" type="int"/>
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| H A D | arm-vfp3.xml | 9 <reg name="d0" bitsize="64" type="float"/>
10 <reg name="d1" bitsize="64" type="float"/>
11 <reg name="d2" bitsize="64" type="float"/>
12 <reg name="d3" bitsize="64" type="float"/>
13 <reg name="d4" bitsize="64" type="float"/>
14 <reg name="d5" bitsize="64" type="float"/>
15 <reg name="d6" bitsize="64" type="float"/>
16 <reg name="d7" bitsize="64" type="float"/>
17 <reg name="d8" bitsize="64" type="float"/>
18 <reg name="d9" bitsize="64" type="float"/>
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| H A D | power-fpu.xml | 10 <reg name="f0" bitsize="64" type="ieee_double" regnum="71"/>
11 <reg name="f1" bitsize="64" type="ieee_double"/>
12 <reg name="f2" bitsize="64" type="ieee_double"/>
13 <reg name="f3" bitsize="64" type="ieee_double"/>
14 <reg name="f4" bitsize="64" type="ieee_double"/>
15 <reg name="f5" bitsize="64" type="ieee_double"/>
16 <reg name="f6" bitsize="64" type="ieee_double"/>
17 <reg name="f7" bitsize="64" type="ieee_double"/>
18 <reg name="f8" bitsize="64" type="ieee_double"/>
19 <reg name="f9" bitsize="64" type="ieee_double"/>
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| H A D | riscv-32bit-fpu.xml | 10 <reg name="ft0" bitsize="32" type="ieee_single"/>
11 <reg name="ft1" bitsize="32" type="ieee_single"/>
12 <reg name="ft2" bitsize="32" type="ieee_single"/>
13 <reg name="ft3" bitsize="32" type="ieee_single"/>
14 <reg name="ft4" bitsize="32" type="ieee_single"/>
15 <reg name="ft5" bitsize="32" type="ieee_single"/>
16 <reg name="ft6" bitsize="32" type="ieee_single"/>
17 <reg name="ft7" bitsize="32" type="ieee_single"/>
18 <reg name="fs0" bitsize="32" type="ieee_single"/>
19 <reg name="fs1" bitsize="32" type="ieee_single"/>
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| H A D | hexagon-core.xml | 19 …<reg name="r00" altname="r0" bitsize="32" offset="0" encoding="uint" format="hex" group="Thread …
20 …<reg name="r01" altname="r1" bitsize="32" offset="4" encoding="uint" format="hex" group="Thread …
21 …<reg name="r02" altname="r2" bitsize="32" offset="8" encoding="uint" format="hex" group="Thread …
22 …<reg name="r03" altname="r3" bitsize="32" offset="12" encoding="uint" format="hex" group="Thread …
23 …<reg name="r04" altname="r4" bitsize="32" offset="16" encoding="uint" format="hex" group="Thread …
24 …<reg name="r05" altname="r5" bitsize="32" offset="20" encoding="uint" format="hex" group="Thread …
25 …<reg name="r06" altname="r6" bitsize="32" offset="24" encoding="uint" format="hex" group="Thread …
26 …<reg name="r07" altname="r7" bitsize="32" offset="28" encoding="uint" format="hex" group="Thread …
27 …<reg name="r08" altname="r8" bitsize="32" offset="32" encoding="uint" format="hex" group="Thread …
28 …<reg name="r09" altname="r9" bitsize="32" offset="36" encoding="uint" format="hex" group="Thread …
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| H A D | loongarch-base64.xml | 10 <reg name="r0" bitsize="64" type="uint64" group="general"/>
11 <reg name="r1" bitsize="64" type="code_ptr" group="general"/>
12 <reg name="r2" bitsize="64" type="data_ptr" group="general"/>
13 <reg name="r3" bitsize="64" type="data_ptr" group="general"/>
14 <reg name="r4" bitsize="64" type="uint64" group="general"/>
15 <reg name="r5" bitsize="64" type="uint64" group="general"/>
16 <reg name="r6" bitsize="64" type="uint64" group="general"/>
17 <reg name="r7" bitsize="64" type="uint64" group="general"/>
18 <reg name="r8" bitsize="64" type="uint64" group="general"/>
19 <reg name="r9" bitsize="64" type="uint64" group="general"/>
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| H A D | loongarch-base32.xml | 10 <reg name="r0" bitsize="32" type="uint32" group="general"/>
11 <reg name="r1" bitsize="32" type="code_ptr" group="general"/>
12 <reg name="r2" bitsize="32" type="data_ptr" group="general"/>
13 <reg name="r3" bitsize="32" type="data_ptr" group="general"/>
14 <reg name="r4" bitsize="32" type="uint32" group="general"/>
15 <reg name="r5" bitsize="32" type="uint32" group="general"/>
16 <reg name="r6" bitsize="32" type="uint32" group="general"/>
17 <reg name="r7" bitsize="32" type="uint32" group="general"/>
18 <reg name="r8" bitsize="32" type="uint32" group="general"/>
19 <reg name="r9" bitsize="32" type="uint32" group="general"/>
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| H A D | riscv-64bit-fpu.xml | 16 <reg name="ft0" bitsize="64" type="riscv_double"/>
17 <reg name="ft1" bitsize="64" type="riscv_double"/>
18 <reg name="ft2" bitsize="64" type="riscv_double"/>
19 <reg name="ft3" bitsize="64" type="riscv_double"/>
20 <reg name="ft4" bitsize="64" type="riscv_double"/>
21 <reg name="ft5" bitsize="64" type="riscv_double"/>
22 <reg name="ft6" bitsize="64" type="riscv_double"/>
23 <reg name="ft7" bitsize="64" type="riscv_double"/>
24 <reg name="fs0" bitsize="64" type="riscv_double"/>
25 <reg name="fs1" bitsize="64" type="riscv_double"/>
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| H A D | power-vsx.xml | 12 <reg name="vs0h" bitsize="64" type="uint64"/>
13 <reg name="vs1h" bitsize="64" type="uint64"/>
14 <reg name="vs2h" bitsize="64" type="uint64"/>
15 <reg name="vs3h" bitsize="64" type="uint64"/>
16 <reg name="vs4h" bitsize="64" type="uint64"/>
17 <reg name="vs5h" bitsize="64" type="uint64"/>
18 <reg name="vs6h" bitsize="64" type="uint64"/>
19 <reg name="vs7h" bitsize="64" type="uint64"/>
20 <reg name="vs8h" bitsize="64" type="uint64"/>
21 <reg name="vs9h" bitsize="64" type="uint64"/>
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| H A D | power-altivec.xml | 22 <reg name="vr0" bitsize="128" type="vec128"/>
23 <reg name="vr1" bitsize="128" type="vec128"/>
24 <reg name="vr2" bitsize="128" type="vec128"/>
25 <reg name="vr3" bitsize="128" type="vec128"/>
26 <reg name="vr4" bitsize="128" type="vec128"/>
27 <reg name="vr5" bitsize="128" type="vec128"/>
28 <reg name="vr6" bitsize="128" type="vec128"/>
29 <reg name="vr7" bitsize="128" type="vec128"/>
30 <reg name="vr8" bitsize="128" type="vec128"/>
31 <reg name="vr9" bitsize="128" type="vec128"/>
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| H A D | s390-vx.xml | 26 <reg name="v0l" bitsize="64" type="uint64"/>
27 <reg name="v1l" bitsize="64" type="uint64"/>
28 <reg name="v2l" bitsize="64" type="uint64"/>
29 <reg name="v3l" bitsize="64" type="uint64"/>
30 <reg name="v4l" bitsize="64" type="uint64"/>
31 <reg name="v5l" bitsize="64" type="uint64"/>
32 <reg name="v6l" bitsize="64" type="uint64"/>
33 <reg name="v7l" bitsize="64" type="uint64"/>
34 <reg name="v8l" bitsize="64" type="uint64"/>
35 <reg name="v9l" bitsize="64" type="uint64"/>
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| H A D | i386-64bit.xml | 40 <reg name="rax" bitsize="64" type="int64" regnum="0"/>
41 <reg name="rbx" bitsize="64" type="int64"/>
42 <reg name="rcx" bitsize="64" type="int64"/>
43 <reg name="rdx" bitsize="64" type="int64"/>
44 <reg name="rsi" bitsize="64" type="int64"/>
45 <reg name="rdi" bitsize="64" type="int64"/>
46 <reg name="rbp" bitsize="64" type="data_ptr"/>
47 <reg name="rsp" bitsize="64" type="data_ptr"/>
48 <reg name="r8" bitsize="64" type="int64"/>
49 <reg name="r9" bitsize="64" type="int64"/>
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| H A D | loongarch-lsx.xml | 27 <reg name="vr0" bitsize="128" type="lsxv" group="lsx"/>
28 <reg name="vr1" bitsize="128" type="lsxv" group="lsx"/>
29 <reg name="vr2" bitsize="128" type="lsxv" group="lsx"/>
30 <reg name="vr3" bitsize="128" type="lsxv" group="lsx"/>
31 <reg name="vr4" bitsize="128" type="lsxv" group="lsx"/>
32 <reg name="vr5" bitsize="128" type="lsxv" group="lsx"/>
33 <reg name="vr6" bitsize="128" type="lsxv" group="lsx"/>
34 <reg name="vr7" bitsize="128" type="lsxv" group="lsx"/>
35 <reg name="vr8" bitsize="128" type="lsxv" group="lsx"/>
36 <reg name="vr9" bitsize="128" type="lsxv" group="lsx"/>
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| H A D | loongarch-lasx.xml | 28 <reg name="xr0" bitsize="256" type="lasxv" group="lasx"/>
29 <reg name="xr1" bitsize="256" type="lasxv" group="lasx"/>
30 <reg name="xr2" bitsize="256" type="lasxv" group="lasx"/>
31 <reg name="xr3" bitsize="256" type="lasxv" group="lasx"/>
32 <reg name="xr4" bitsize="256" type="lasxv" group="lasx"/>
33 <reg name="xr5" bitsize="256" type="lasxv" group="lasx"/>
34 <reg name="xr6" bitsize="256" type="lasxv" group="lasx"/>
35 <reg name="xr7" bitsize="256" type="lasxv" group="lasx"/>
36 <reg name="xr8" bitsize="256" type="lasxv" group="lasx"/>
37 <reg name="xr9" bitsize="256" type="lasxv" group="lasx"/>
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| /qemu/include/hw/ |
| H A D | registerfields.h | 21 #define REG32(reg, addr) \ argument
22 enum { A_ ## reg = (addr) }; \
23 enum { R_ ## reg = (addr) / 4 };
25 #define REG8(reg, addr) \ argument
26 enum { A_ ## reg = (addr) }; \
27 enum { R_ ## reg = (addr) };
29 #define REG16(reg, addr) \ argument
30 enum { A_ ## reg = (addr) }; \
31 enum { R_ ## reg = (addr) / 2 };
33 #define REG64(reg, addr) \ argument
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| /qemu/target/sh4/ |
| H A D | translate.c | 328 static inline void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) in gen_load_fpr64() argument
331 tcg_debug_assert((reg & 1) == 0); in gen_load_fpr64()
332 reg ^= ctx->fbank; in gen_load_fpr64()
333 tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]); in gen_load_fpr64()
336 static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) in gen_store_fpr64() argument
339 tcg_debug_assert((reg & 1) == 0); in gen_store_fpr64()
340 reg ^= ctx->fbank; in gen_store_fpr64()
341 tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t); in gen_store_fpr64()
354 #define REG(x) cpu_gregs[(x) ^ ctx->gbank] macro
496 tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); in _decode_opc()
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