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/linux-6.8/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10_socdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
10 compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
25 led-hps0 {
30 led-hps1 {
35 led-hps2 {
43 /* We expect the bootloader to fill in the reg */
44 reg = <0 0x80000000 0 0>;
47 ref_033v: regulator-v-ref {
[all …]
/linux-6.8/arch/powerpc/boot/dts/fsl/
Dc293si-post.dtsi14 * names of its contributors may be used to endorse or promote products
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
44 compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
53 reg = <0 0 0 0 0>;
[all …]
Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
14 * names of its contributors may be used to endorse or promote products
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_s7_1d>;
64 phy-connection-type = "sgmii";
[all …]
/linux-6.8/Documentation/devicetree/bindings/i3c/
Di3c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - Miquel Raynal <miquel.raynal@bootlin.com>
20 pattern: "^i3c-master@[0-9a-f]+$"
22 "#address-cells":
39 "#size-cells":
42 i3c-scl-hz:
49 i2c-scl-hz:
[all …]
/linux-6.8/arch/arm/boot/dts/microchip/
Dsama5d3_gmac.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * sama5d3_gmac.dtsi - Device Tree Include file for SAMA5D3 SoC with
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
67 compatible = "atmel,sama5d3-gem";
68 reg = <0xf0028000 0x100>;
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
73 clock-names = "hclk", "pclk";
Dsama5d3xdm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sama5d3dm.dtsi - Device Tree file for SAMA5 display module
15 reg = <0x1b>;
16 interrupt-parent = <&pioE>;
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_qt1070_irq>;
20 wakeup-source;
25 atmel,adc-ts-wires = <4>;
26 atmel,adc-ts-pressure-threshold = <10000>;
/linux-6.8/drivers/pinctrl/
Dpinctrl-single.c25 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/platform_data/pinctrl-single.h>
37 #define DRIVER_NAME "pinctrl-single"
41 * struct pcs_func_vals - mux function register offset and value pair
42 * @reg: register virtual address
47 void __iomem *reg; member
53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
70 * struct pcs_conf_type - pinconf property name, pinconf param pair
80 * struct pcs_function - pinctrl function
84 * @pgnames: array of pingroup names the function uses
[all …]
/linux-6.8/drivers/scsi/aic7xxx/
Daic7xxx_osm_pci.c4 * Copyright (c) 2000-2001 Adaptec Inc.
18 * 3. Neither the names of the above-listed copyright holders nor the names
148 if (ahc->platform_data && ahc->platform_data->host) in ahc_linux_pci_dev_remove()
149 scsi_remove_host(ahc->platform_data->host); in ahc_linux_pci_dev_remove()
160 struct pci_dev *pdev = ahc->dev_softc, *master_pdev; in ahc_linux_pci_inherit_flags()
161 unsigned int master_devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0); in ahc_linux_pci_inherit_flags()
163 master_pdev = pci_get_slot(pdev->bus, master_devfn); in ahc_linux_pci_inherit_flags()
167 ahc->flags &= ~AHC_BIOS_ENABLED; in ahc_linux_pci_inherit_flags()
168 ahc->flags |= master->flags & AHC_BIOS_ENABLED; in ahc_linux_pci_inherit_flags()
170 ahc->flags &= ~AHC_PRIMARY_CHANNEL; in ahc_linux_pci_inherit_flags()
[all …]
/linux-6.8/arch/arm/boot/dts/rockchip/
Drk3288-veyron-jerry.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron-chromebook.dtsi"
10 #include "../cros-ec-sbs.dtsi"
14 compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14",
15 "google,veyron-jerry-rev13", "google,veyron-jerry-rev12",
16 "google,veyron-jerry-rev11", "google,veyron-jerry-rev10",
17 "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
18 "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
19 "google,veyron-jerry-rev3", "google,veyron-jerry",
[all …]
/linux-6.8/Documentation/devicetree/bindings/mfd/
Dbrcm,bcm6368-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
18 "#address-cells": true
20 "#size-cells": true
24 - const: brcm,bcm6368-gpio-sysctl
25 - const: syscon
[all …]
/linux-6.8/Documentation/devicetree/bindings/clock/ti/
Ddivider.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped adjustable clock rate divider that does not gate and has
17 ti,index-starts-at-one - valid divisor values start at 1, not the default
24 ti,index-power-of-two - valid divisor values are powers of two. E.g:
41 Any zero value in this array means the corresponding bit-value is invalid
52 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
56 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
57 - #clock-cells : from common clock binding; shall be set to 0.
58 - clocks : link to phandle of parent clock
59 - reg : offset for register controlling adjustable divider
[all …]
/linux-6.8/arch/arm/boot/dts/marvell/
Darmada-xp-openblocks-ax3-4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for OpenBlocks AX3-4 board
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include "armada-xp-mv78260.dtsi"
16 model = "PlatHome OpenBlocks AX3-4 board";
17 …compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell…
20 stdout-path = "serial0:115200n8";
[all …]
Dkirkwood-nsa310a.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "kirkwood-nsa3x0-common.dtsi"
12 compatible = "zyxel,nsa310a", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood";
16 reg = <0x00000000 0x10000000>;
21 stdout-path = &uart0;
25 pinctrl: pin-controller@10000 {
26 pinctrl-names = "default";
28 pmx_led_esata_green: pmx-led-esata-green {
33 pmx_led_esata_red: pmx-led-esata-red {
[all …]
/linux-6.8/drivers/pinctrl/freescale/
Dpinctrl-imx8ulp.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "pinctrl-imx.h"
115 /* Pad names for the pinmux subsystem */
226 u32 reg; in imx8ulp_pmx_gpio_set_direction() local
228 pin_reg = &ipctl->pin_regs[offset]; in imx8ulp_pmx_gpio_set_direction()
229 if (pin_reg->mux_reg == -1) in imx8ulp_pmx_gpio_set_direction()
230 return -EINVAL; in imx8ulp_pmx_gpio_set_direction()
232 reg = readl(ipctl->base + pin_reg->mux_reg); in imx8ulp_pmx_gpio_set_direction()
234 reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED; in imx8ulp_pmx_gpio_set_direction()
236 reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED; in imx8ulp_pmx_gpio_set_direction()
[all …]
/linux-6.8/Documentation/devicetree/bindings/clock/
Dfujitsu,mb86s70-crg11.txt2 -----------------------------------
5 - compatible : Shall contain "fujitsu,mb86s70-crg11"
6 - #clock-cells : Shall be 3 {cntrlr domain port}
13 compatible = "fujitsu,mb86s70-crg11";
14 #clock-cells = <3>;
18 #mbox-cells = <1>;
20 reg = <0 0x2B1F0000 0x1000>;
21 interrupts = <0 36 4>, /* LP Non-Sec */
22 <0 35 4>, /* HP Non-Sec */
25 clock-names = "clk";
/linux-6.8/arch/arm64/boot/dts/qcom/
Dsdm845-lg-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
16 /delete-node/ &adsp_mem;
17 /delete-node/ &cdsp_mem;
18 /delete-node/ &gpu_mem;
19 /delete-node/ &ipa_fw_mem;
20 /delete-node/ &mba_region;
21 /delete-node/ &mpss_region;
[all …]
Dsdm845-shift-axolotl.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
20 qcom,msm-id = <321 0x20001>;
21 qcom,board-id = <11 0>;
30 #address-cells = <2>;
31 #size-cells = <2>;
34 stdout-path = "serial0";
[all …]
/linux-6.8/arch/riscv/boot/dts/allwinner/
Dsun20i-d1-lichee-rv-86-panel-480p.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include "sun20i-d1-lichee-rv-86-panel.dtsi"
8 compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
9 "allwinner,sun20i-d1";
13 pinctrl-0 = <&i2c2_pb0_pins>;
14 pinctrl-names = "default";
19 reg = <0x48>;
20 interrupt-parent = <&pio>;
22 iovcc-supply = <&reg_vcc_3v3>;
23 reset-gpios = <&pio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */
[all …]
/linux-6.8/Documentation/devicetree/bindings/watchdog/
Dzii,rave-sp-wdt.txt7 Documentation/devicetree/bindings/mfd/zii,rave-sp.txt)
11 - compatible: Depending on wire protocol implemented by RAVE SP
13 - "zii,rave-sp-watchdog"
14 - "zii,rave-sp-watchdog-legacy"
18 - wdt-timeout: Two byte nvmem cell specified as per
23 rave-sp {
24 compatible = "zii,rave-sp-rdu1";
25 current-speed = <38400>;
28 wdt_timeout: wdt-timeout@8E {
29 reg = <0x8E 2>;
[all …]
/linux-6.8/arch/arm/boot/dts/renesas/
Dr8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * the iWave-RZ/G1H Qseven board development platform connected with the
10 #include <dt-bindings/media/video-interfaces.h>
19 reg = <0x3c>;
21 clock-names = "xclk";
22 AVDD-supply = <&reg_2p8v>;
23 DOVDD-supply = <&reg_2p8v>;
24 DVDD-supply = <&reg_1p8v>;
29 bus-width = <8>;
30 data-shift = <2>;
[all …]
/linux-6.8/arch/arm64/boot/dts/renesas/
Dr8a77965-salvator-xs.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-N
8 /dts-v1/;
10 #include "salvator-xs.dtsi"
13 model = "Renesas Salvator-X 2nd version board based on r8a77965";
14 compatible = "renesas,salvator-xs", "renesas,r8a77965";
19 reg = <0x0 0x48000000 0x0 0x78000000>;
30 clock-names = "du.0", "du.1", "du.3",
Dr8a77965-salvator-x.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Salvator-X board with R-Car M3-N
8 /dts-v1/;
10 #include "salvator-x.dtsi"
13 model = "Renesas Salvator-X board based on r8a77965";
14 compatible = "renesas,salvator-x", "renesas,r8a77965";
19 reg = <0x0 0x48000000 0x0 0x78000000>;
30 clock-names = "du.0", "du.1", "du.3",
Dr8a77965-ulcb.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board with R-Car M3-N
9 /dts-v1/;
20 reg = <0x0 0x48000000 0x0 0x78000000>;
31 clock-names = "du.0", "du.1", "du.3",
/linux-6.8/arch/arm/boot/dts/nxp/vf/
Dvf610m4-colibri.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Device tree for Colibri VF61 Cortex-M4 support
8 /dts-v1/;
12 model = "VF610 Cortex-M4";
17 stdout-path = "serial2:115200";
22 reg = <0x8c000000 0x3000000>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_uart2>;
53 vf610-colibri {
/linux-6.8/arch/arm/boot/dts/samsung/
Dexynos4412-n710x.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3 #include "exynos4412-midas.dtsi"
7 model = "Samsung Galaxy Note 2 (GT-N7100, GT-N7105) based on Exynos4412";
8 chassis-type = "handset";
12 reg = <0x40000000 0x80000000>;
17 cam_vdda_reg: voltage-regulator-10 {
18 compatible = "regulator-fixed";
19 regulator-name = "CAM_SENSOR_CORE_1.2V";
20 regulator-min-microvolt = <1200000>;
[all …]

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