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/linux-6.8/drivers/clk/sunxi/
Dclk-a20-gmac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
25 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
40 * driver then responds by auto-reparenting the clock.
57 const char *clk_name = node->name; in sun7i_a20_gmac_clk_setup()
[all …]
/linux-6.8/arch/powerpc/boot/dts/fsl/
Dbsc9132qds.dtsi2 * BSC9132 QDS Device Tree Source stub (no addresses or top-level ranges)
14 * names of its contributors may be used to endorse or promote products
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
46 #address-cells = <1>;
47 #size-cells = <1>;
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Dpq3-sec4.4-0.dtsi14 * names of its contributors may be used to endorse or promote products
36 compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
41 reg = <0x30000 0x10000>;
45 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
51 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
52 reg = <0x2000 0x1000>;
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Dt1042d4rdb.dts14 * names of its contributors may be used to endorse or promote products
35 /include/ "t104xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
47 compatible = "fsl,t1040d4rdb-cpld",
48 "fsl,deepsleep-cpld";
55 phy-handle = <&phy_sgmii_0>;
56 phy-connection-type = "sgmii";
60 phy-handle = <&phy_sgmii_1>;
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Dpq3-mpic.dtsi14 * names of its contributors may be used to endorse or promote products
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
39 reg = <0x40000 0x40000>;
41 device_type = "open-pic";
42 big-endian;
43 single-cpu-affinity;
44 last-interrupt-source = <255>;
48 compatible = "fsl,mpic-global-timer";
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/linux-6.8/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Jitao shi <jitao.shi@mediatek.com>
24 - mediatek,mt8188-dp-tx
25 - mediatek,mt8188-edp-tx
26 - mediatek,mt8195-dp-tx
27 - mediatek,mt8195-edp-tx
29 reg:
[all …]
/linux-6.8/Documentation/devicetree/bindings/serial/
Dnxp,sc16is7xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP SC16IS7xx Advanced Universal Asynchronous Receiver-Transmitter (UART)
10 - Hugo Villeneuve <hvilleneuve@dimonoff.com>
15 - nxp,sc16is740
16 - nxp,sc16is741
17 - nxp,sc16is750
18 - nxp,sc16is752
19 - nxp,sc16is760
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/linux-6.8/Documentation/devicetree/bindings/display/bridge/
Dite,it66121.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Phong LE <ple@baylibre.com>
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The IT66121 is a high-performance and low-power single channel HDMI
21 - ite,it66121
22 - ite,it6610
24 reg:
27 reset-gpios:
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/linux-6.8/arch/mips/boot/dts/mscc/
Docelot_pcb120.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
12 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
15 stdout-path = "serial0:115200n8";
20 reg = <0x0 0x0e000000>;
25 phy_int_pins: phy-int-pins {
30 phy_load_save_pins: phy-load-save-pins {
[all …]
/linux-6.8/Documentation/devicetree/bindings/pwm/
Dpwm-lp3943.txt4 - compatible: "ti,lp3943-pwm"
5 - #pwm-cells: Should be 2. See pwm.yaml in this directory for a
9 - ti,pwm0 or ti,pwm1: Output pin number(s) for PWM channel 0 or 1.
23 reg = <0x60>;
30 compatible = "ti,lp3943-pwm";
31 #pwm-cells = <2>;
41 compatible = "pwm-leds";
45 max-brightness = <255>;
53 reg = <0x2c>;
56 pwm-names = "lp8557";
/linux-6.8/Documentation/devicetree/bindings/pinctrl/
Dbrcm,nsp-pinmux.txt7 - compatible:
8 Must be "brcm,nsp-pinmux"
10 - reg:
15 - function:
18 - groups:
22 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
27 compatible = "brcm,nsp-pinmux";
28 reg = <0x1803f1c0 0x04>,
32 pinctrl-names = "default";
33 pinctrl-0 = <&pwm>, <&gpio_b>, <&nand_sel>;
Dmicrochip,pic32-pinctrl.txt3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
12 - compatible: "microchip,pic32mada-pinctrl"
13 - reg: Address range of the pinctrl registers.
14 - clocks: Clock specifier (see clock bindings for details)
16 Required properties for pin configuration sub-nodes:
17 - pins: List of pins to which the configuration applies.
19 Optional properties for pin configuration sub-nodes:
20 ----------------------------------------------------
21 - function: Mux function for the specified pins.
[all …]
Dmediatek,mt7622-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
18 - mediatek,mt7622-pinctrl
19 - mediatek,mt7629-pinctrl
21 reg:
24 reg-names:
26 - const: eint
[all …]
/linux-6.8/tools/perf/arch/mips/include/
Ddwarf-regs-table.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * dwarf-regs-table.h : Mapping of DWARF debug register numbers into
4 * register names.
22 #define REG_DWARFNUM_NAME(reg, idx) [idx] = "$" #reg argument
/linux-6.8/Documentation/devicetree/bindings/mtd/
Dmtd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
19 User-defined MTD device name. Can be used to assign user friendly
20 names to MTD devices (instead of the flash model or flash controller
24 '#address-cells':
27 '#size-cells':
34 - compatible
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/linux-6.8/arch/arm64/boot/dts/qcom/
Dipq5332-rdp468.dts1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 /dts-v1/;
10 #include "ipq5332-rdp-common.dtsi"
14 compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332";
16 regulator_fixed_5p0: regulator-s0500 {
17 compatible = "regulator-fixed";
18 regulator-min-microvolt = <500000>;
19 regulator-max-microvolt = <500000>;
20 regulator-boot-on;
[all …]
/linux-6.8/arch/arm64/boot/dts/freescale/
Dimx8mp-skov-revb-mi1010ait-1cp1.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 /dts-v1/;
5 #include "imx8mp-skov-reva.dtsi"
8 model = "SKOV IMX8MP CPU revB - MI1010AIT-1CP1";
9 compatible = "skov,imx8mp-skov-revb-mi1010ait-1cp1", "fsl,imx8mp";
12 compatible = "multi-inno,mi1010ait-1cp";
14 power-supply = <&reg_tft_vcom>;
18 remote-endpoint = <&ldb_lvds_ch0>;
29 clock-frequency = <100000>;
30 pinctrl-names = "default";
[all …]
Dfsl-ls1028a-kontron-sl28-var3-ads2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board on a SMARC Eval 2.0
10 /dts-v1/;
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls1028a-kontron-sl28.dts"
16 model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier";
17 compatible = "kontron,sl28-var3-ads2", "kontron,sl28-var3",
20 pwm-fan {
21 compatible = "pwm-fan";
22 cooling-min-state = <0>;
[all …]
/linux-6.8/arch/arm64/boot/dts/renesas/
Dsalvator-xs.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Salvator-X 2nd version board
5 * Copyright (C) 2015-2017 Renesas Electronics Corp.
8 #include "salvator-common.dtsi"
11 model = "Renesas Salvator-X 2nd version board";
12 compatible = "renesas,salvator-xs";
16 clock-frequency = <16640000>;
20 clock-frequency = <400000>;
22 versaclock6: clock-generator@6a {
24 reg = <0x6a>;
[all …]
/linux-6.8/arch/arm/boot/dts/renesas/
Dgr-peach-audiocamerashield.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the GR-Peach audiocamera shield expansion board
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
13 /* On-board camera clock. */
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <27000000>;
28 /* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */
44 pinctrl-names = "default";
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/linux-6.8/Documentation/devicetree/bindings/net/
Dbrcm,bcmgenet.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Doug Berger <opendmb@gmail.com>
11 - Florian Fainelli <f.fainelli@gmail.com>
16 - brcm,genet-v1
17 - brcm,genet-v2
18 - brcm,genet-v3
19 - brcm,genet-v4
20 - brcm,genet-v5
[all …]
/linux-6.8/arch/arm/boot/dts/ti/omap/
Domap3-evm-37xx.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "omap3-evm-common.dtsi"
9 #include "omap3-evm-processor-common.dtsi"
13 compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3";
17 pinctrl-names = "default";
18 pinctrl-0 = <&hsusb2_2_pins>;
20 ehci_phy_pins: ehci-phy-pins {
21 pinctrl-single,pins = <
[all …]
/linux-6.8/arch/arm/boot/dts/marvell/
Darmada-xp-db-dxbc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for DB-DXBC2 board
7 * Based on armada-xp-db.dts
12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 /dts-v1/;
20 #include "armada-xp-98dx4251.dtsi"
24 compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";
32 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
43 devbus,bus-width = <16>;
44 devbus,turn-off-ps = <60000>;
[all …]
/linux-6.8/Documentation/devicetree/bindings/gpio/
Dsifive,gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Walmsley <paul.walmsley@sifive.com>
15 - enum:
16 - sifive,fu540-c000-gpio
17 - sifive,fu740-c000-gpio
18 - canaan,k210-gpiohs
19 - const: sifive,gpio0
21 reg:
[all …]
/linux-6.8/Documentation/devicetree/bindings/display/panel/
Dnovatek,nt36672a.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Semwal <sumit.semwal@linaro.org>
19 - $ref: panel-common.yaml#
24 - enum:
25 - tianma,fhd-video
26 - const: novatek,nt36672a
32 reset-gpios:
34 description: phandle of gpio for reset line - This should be 8mA, gpio
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