Home
last modified time | relevance | path

Searched +full:reg +full:- +full:names (Results 3051 – 3075 of 3936) sorted by relevance

1...<<121122123124125126127128129130>>...158

/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h5-nanopi-neo2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
5 #include "sun50i-h5.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
11 compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
19 stdout-path = "serial0:115200n8";
23 compatible = "gpio-leds";
28 default-state = "on";
37 reg_gmac_3v3: gmac-3v3 {
38 compatible = "regulator-fixed";
[all …]
Dsun50i-h6-beelink-gs1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
6 #include "sun50i-h6.dtsi"
7 #include "sun50i-h6-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
13 compatible = "azw,beelink-gs1", "allwinner,sun50i-h6";
21 stdout-path = "serial0:115200n8";
25 compatible = "hdmi-connector";
27 ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
31 remote-endpoint = <&hdmi_out_con>;
[all …]
/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-gxl-s905x-libretech-cc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/sound/meson-aiu.h>
13 #include "meson-gxl-s905x.dtsi"
16 compatible = "libretech,aml-s905x-cc", "amlogic,s905x",
17 "amlogic,meson-gxl";
18 model = "Libre Computer AML-S905X-CC";
25 dio2133: analog-amplifier {
26 compatible = "simple-audio-amplifier";
[all …]
/linux-5.10/arch/arm/boot/dts/
Dam335x-netcom-plus-2xx.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
13 #include "am335x-baltos.dtsi"
14 #include "am335x-baltos-leds.dtsi"
22 pinctrl-single,pins = <
35 pinctrl-single,pins = <
58 pinctrl-names = "default";
59 pinctrl-0 = <&uart1_pins>;
60 dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
[all …]
Dsun5i-a10s-wobo-i5.dts4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "sun5i-a10s.dtsi"
45 #include "sunxi-common-regulators.dtsi"
47 #include <dt-bindings/gpio/gpio.h>
48 #include <dt-bindings/interrupt-controller/irq.h>
51 model = "A10s-Wobo i5";
52 compatible = "wobo,a10s-wobo-i5", "allwinner,sun5i-a10s";
59 stdout-path = "serial0:115200n8";
63 compatible = "gpio-leds";
[all …]
Dsun5i-a13-empire-electronix-d709.dts4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "sun5i-a13.dtsi"
45 #include "sunxi-common-regulators.dtsi"
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/input/input.h>
48 #include <dt-bindings/interrupt-controller/irq.h>
49 #include <dt-bindings/pwm/pwm.h>
53 compatible = "empire-electronix,d709", "allwinner,sun5i-a13";
60 compatible = "pwm-backlight";
[all …]
Dat91sam9x5_lcd.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,at91sam9x5-hlcdc";
17 reg = <0xf8038000 0x4000>;
20 clock-names = "periph_clk","sys_clk", "slow_clk";
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
[all …]
Dam335x-bonegreen-wireless.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "am335x-bone-common.dtsi"
9 #include "am335x-bonegreen-common.dtsi"
10 #include <dt-bindings/interrupt-controller/irq.h>
14 …compatible = "ti,am335x-bone-green-wireless", "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,…
17 compatible = "regulator-fixed";
18 regulator-name = "wlan-en-regulator";
19 regulator-min-microvolt = <1800000>;
[all …]
Dmt8127.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 interrupt-parent = <&sysirq>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 enable-method = "mediatek,mt81xx-tz-smp";
24 compatible = "arm,cortex-a7";
[all …]
Darmada-xp-mv78260.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
33 reg = <0>;
35 clock-latency = <1000000>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/opp/
Dqcom-nvmem-cpufreq.txt8 defines the voltage and frequency value based on the msm-id in SMEM
10 The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
13 operating-points-v2 table when it is parsed by the OPP framework.
16 --------------------
18 - operating-points-v2: Phandle to the operating-points-v2 table to use.
20 In 'operating-points-v2' table:
21 - compatible: Should be
22 - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
26 --------------------
28 - power-domains: A phandle pointing to the PM domain specifier which provides
[all …]
/linux-5.10/Documentation/devicetree/bindings/power/supply/
Dqcom_smbb.txt1 Qualcomm Switch-Mode Battery Charger and Boost
4 - compatible:
8 - "qcom,pm8941-charger"
10 - reg:
12 Value type: <prop-encoded-array>
15 - interrupts:
17 Value type: <prop-encoded-array>
21 - charge done
22 - charge fast mode
23 - charge trickle mode
[all …]
/linux-5.10/Documentation/devicetree/bindings/soundwire/
Dqcom,sdw.txt7 - compatible:
10 Definition: must be "qcom,soundwire-v<MAJOR>.<MINOR>.<STEP>",
12 "qcom,soundwire-v1.3.0"
13 "qcom,soundwire-v1.5.0"
14 "qcom,soundwire-v1.5.1"
15 "qcom,soundwire-v1.6.0"
16 - reg:
18 Value type: <prop-encoded-array>
22 - interrupts:
24 Value type: <prop-encoded-array>
[all …]
/linux-5.10/include/trace/
Ddefine_trace.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * define_trace.h, not the file including it. Full path names for out of tree
41 assign, print, reg, unreg) \ argument
42 DEFINE_TRACE_FN(name, reg, unreg, PARAMS(proto), PARAMS(args))
46 assign, print, reg, unreg) \ argument
47 DEFINE_TRACE_FN(name, reg, unreg, PARAMS(proto), PARAMS(args))
60 #define DEFINE_EVENT_FN(template, name, proto, args, reg, unreg) \ argument
61 DEFINE_TRACE_FN(name, reg, unreg, PARAMS(proto), PARAMS(args))
/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra114-pinmux.txt4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: "nvidia,tegra114-pinmux"
10 - reg: Should contain the register physical address and length for each of
16 - nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
17 - nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
18 - nvidia,lock: Integer. Lock the pin configuration against further changes
20 - nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
21 - nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high.
22 - nvidia,drive-type: Integer. Valid range 0...3.
[all …]
/linux-5.10/drivers/clk/keystone/
Dgate.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Murali Karicheri <m-karicheri2@ti.com>
9 #include <linux/clk-provider.h>
44 * struct clk_psc_data - PSC data
56 * struct clk_psc - PSC clock structure
96 } while (((ptstat >> domain_id) & 1) && count--); in psc_config()
101 } while (!((mdstat & MDSTAT_STATE_MASK) == next_state) && count--); in psc_config()
107 struct clk_psc_data *data = psc->psc_data; in keystone_clk_is_enabled()
108 u32 mdstat = readl(data->control_base + MDSTAT); in keystone_clk_is_enabled()
116 struct clk_psc_data *data = psc->psc_data; in keystone_clk_enable()
[all …]
/linux-5.10/arch/powerpc/boot/dts/fsl/
Dp1020mbg-pc.dtsi2 * P1020 MBG-PC Device Tree Source stub (no addresses or top-level ranges)
14 * names of its contributors may be used to endorse or promote products
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x4000000>;
41 bank-width = <2>;
42 device-width = <1>;
46 reg = <0x0 0x00020000>;
52 reg = <0x00020000 0x003e0000>;
[all …]
Dp1024rdb_32b.dts14 * names of its contributors may be used to endorse or promote products
35 /include/ "p1020si-pre.dtsi"
45 reg = <0x0 0xffe05000 0 0x1000>;
55 reg = <0x0 0xffe09000 0 0x1000>;
70 reg = <0x0 0xffe0a000 0 0x1000>;
74 reg = <0x0 0x0 0x0 0x0 0x0>;
87 /include/ "p1020si-post.dtsi"
Dp1024rdb_36b.dts14 * names of its contributors may be used to endorse or promote products
35 /include/ "p1020si-pre.dtsi"
45 reg = <0xf 0xffe05000 0 0x1000>;
55 reg = <0xf 0xffe09000 0 0x1000>;
70 reg = <0xf 0xffe0a000 0 0x1000>;
74 reg = <0x0 0x0 0x0 0x0 0x0>;
87 /include/ "p1020si-post.dtsi"
Dinterlaken-lac-portals.dtsi13 * names of its contributors may be used to endorse or promote products
34 #address-cells = <0x1>;
35 #size-cells = <0x1>;
36 compatible = "fsl,interlaken-lac-portals";
38 lportal0: lac-portal@0 {
39 compatible = "fsl,interlaken-lac-portal-v1.0";
40 reg = <0x0 0x1000>;
43 lportal1: lac-portal@1000 {
44 compatible = "fsl,interlaken-lac-portal-v1.0";
45 reg = <0x1000 0x1000>;
[all …]
Dqoriq-sec4.2-0.dtsi14 * names of its contributors may be used to endorse or promote products
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
45 compatible = "fsl,sec-v4.2-job-ring",
46 "fsl,sec-v4.0-job-ring";
47 reg = <0x1000 0x1000>;
52 compatible = "fsl,sec-v4.2-job-ring",
[all …]
Dqoriq-sec5.0-0.dtsi14 * names of its contributors may be used to endorse or promote products
36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
45 compatible = "fsl,sec-v5.0-job-ring",
46 "fsl,sec-v4.0-job-ring";
47 reg = <0x1000 0x1000>;
52 compatible = "fsl,sec-v5.0-job-ring",
[all …]
/linux-5.10/drivers/clk/
Dclk-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
13 #include <linux/clk-provider.h>
49 void __iomem *reg; member
63 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()
81 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
83 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate()
84 if (pllclk->type == PLL_TYPE_PCP) { in xgene_clk_pll_recalc_rate()
113 pllclk->version); in xgene_clk_pll_recalc_rate()
125 unsigned long flags, void __iomem *reg, u32 pll_offset, in xgene_register_clk_pll() argument
[all …]
/linux-5.10/drivers/of/unittest-data/
Doverlay_gpio_02a.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <0>;
9 compatible = "unittest-gpio";
10 reg = <2>;
11 gpio-controller;
12 #gpio-cells = <2>;
14 gpio-line-names = "line-A", "line-B";
/linux-5.10/include/linux/gpio/
Dgpio-reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 struct gpio_chip *gpio_reg_init(struct device *dev, void __iomem *reg,
10 const char *const *names, struct irq_domain *irqdom, const int *irqs);

1...<<121122123124125126127128129130>>...158