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/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-orion.txt4 - compatible : should be on of the following:
5 - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs
6 - "marvell,armada-370-spi", for the Armada 370 SoCs
7 - "marvell,armada-375-spi", for the Armada 375 SoCs
8 - "marvell,armada-380-spi", for the Armada 38x SoCs
9 - "marvell,armada-390-spi", for the Armada 39x SoCs
10 - "marvell,armada-xp-spi", for the Armada XP SoCs
11 - reg : offset and length of the register set for the device.
19 chip-select lines 0 through 7 respectively.
20 - cell-index : Which of multiple SPI controllers is this.
[all …]
/linux-5.10/arch/arm/boot/dts/
Domap3-cm-t3517.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Support for CompuLab CM-T3517
5 /dts-v1/;
8 #include "omap3-cm-t3x.dtsi"
11 model = "CompuLab CM-T3517";
12 compatible = "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
14 vmmc: regulator-vmmc {
15 compatible = "regulator-fixed";
16 regulator-name = "vmmc";
17 regulator-min-microvolt = <3300000>;
[all …]
Dimx6qdl-tqma6a.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
8 pinctrl-names = "default";
9 pinctrl-0 = <&pinctrl_i2c1>;
10 clock-frequency = <100000>;
15 reg = <0x08>;
20 reg = <0x48>;
25 reg = <0x50>;
Dimx6qdl-tqma6b.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
8 pinctrl-names = "default";
9 pinctrl-0 = <&pinctrl_i2c3>;
10 clock-frequency = <100000>;
15 reg = <0x08>;
20 reg = <0x48>;
25 reg = <0x50>;
Dexynos3250-artik5.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
21 stdout-path = &serial_2;
26 reg = <0x40000000 0x1f800000>;
30 compatible = "samsung,secure-firmware";
31 reg = <0x0205f000 0x1000>;
34 thermal-zones {
35 cpu_thermal: cpu-thermal {
[all …]
Dkirkwood-l-50.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Check Point L-50 Board Description
7 /dts-v1/;
10 #include "kirkwood-6281.dtsi"
13 model = "Check Point L-50";
14 compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood";
18 reg = <0x00000000 0x20000000>;
23 stdout-path = &uart0;
27 pinctrl: pin-controller@10000 {
28 pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>;
[all …]
Dam571x-idk.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include "dra7-mmc-iodelay.dtsi"
11 #include "dra72x-mmc-iodelay.dtsi"
12 #include "am57xx-idk-common.dtsi"
13 #include "dra7-ipu-dsp-common.dtsi"
17 compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7";
[all …]
Darmada-385-clearfog-gtr-l8.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 #include "armada-385-clearfog-gtr.dtsi"
12 reg = <4>;
13 pinctrl-names = "default";
14 pinctrl-0 = <&cf_gtr_switch_reset_pins>;
15 reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 reg = <1>;
24 phy-handle = <&switch0phy0>;
[all …]
Dgemini-dlink-dir-685.dts2 * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
5 /dts-v1/;
8 #include <dt-bindings/input/input.h>
11 model = "D-Link DIR-685 Xtreme N Storage Router";
12 compatible = "dlink,dir-685", "cortina,gemini";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
19 reg = <0x00000000 0x8000000>;
24 stdout-path = "uart0:19200n8";
[all …]
Dimx6ull-myir-mys-6ulx.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pwm/pwm.h>
12 model = "MYiR MYS-6ULX Single Board Computer";
16 stdout-path = &uart1;
19 reg_vdd_5v: regulator-vdd-5v {
20 compatible = "regulator-fixed";
21 regulator-name = "VDD_5V";
22 regulator-min-microvolt = <5000000>;
[all …]
Dstm32f769-disco.dts2 * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
45 #include "stm32f769-pinctrl.dtsi"
46 #include <dt-bindings/input/input.h>
47 #include <dt-bindings/gpio/gpio.h>
50 model = "STMicroelectronics STM32F769-DISCO board";
51 compatible = "st,stm32f769-disco", "st,stm32f769";
55 stdout-path = "serial0:115200n8";
60 reg = <0xC0000000 0x1000000>;
[all …]
Dam5729-beagleboneai.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/
6 /dts-v1/;
9 #include "am57xx-commercial-grade.dtsi"
10 #include "dra74x-mmc-iodelay.dtsi"
11 #include "dra74-ipu-dsp-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/dra.h>
18 compatible = "beagle,am5729-beagleboneai", "ti,am5728",
[all …]
Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra20-cpu-opp.dtsi"
10 #include "tegra20-cpu-opp-microvolt.dtsi"
31 * pre-existing /chosen node to be available to insert the
37 reg = <0x00000000 0x40000000>;
40 reserved-memory {
[all …]
Dexynos5420-smdk5420.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "exynos5420-cpus.dtsi"
12 #include <dt-bindings/clock/samsung,s2mps11.h>
13 #include <dt-bindings/gpio/gpio.h>
21 reg = <0x20000000 0x80000000>;
26 stdout-path = "serial2:115200n8";
29 fixed-rate-clocks {
31 compatible = "samsung,exynos5420-oscclk";
32 clock-frequency = <24000000>;
[all …]
Dimx53-tx53-x03x.dts2 * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
4 * This file is dual-licensed: you can use it either under the terms
42 /dts-v1/;
43 #include "imx53-tx53.dtsi"
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/pwm/pwm.h>
49 model = "Ka-Ro electronics TX53 module (LCD)";
57 compatible = "fsl,imx-parallel-display";
58 interface-pix-fmt = "rgb24";
[all …]
Dmmp2-olpc-xo-1-75.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/linux-event-codes.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
15 model = "OLPC XO-1.75";
16 compatible = "olpc,xo-1.75", "mrvl,mmp2";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 compatible = "simple-framebuffer";
[all …]
/linux-5.10/sound/soc/tegra/
Dtegra210_admaif.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra210_admaif.c - Tegra ADMAIF driver
20 #define CH_REG(offset, reg, id) \ argument
21 ((offset) + (reg) + (TEGRA_ADMAIF_CHANNEL_REG_STRIDE * (id)))
23 #define CH_TX_REG(reg, id) CH_REG(admaif->soc_data->tx_base, reg, id) argument
25 #define CH_RX_REG(reg, id) CH_REG(admaif->soc_data->rx_base, reg, id) argument
36 REG_DEFAULTS((id) - 1, \
80 static bool tegra_admaif_wr_reg(struct device *dev, unsigned int reg) in tegra_admaif_wr_reg() argument
84 unsigned int num_ch = admaif->soc_data->num_ch; in tegra_admaif_wr_reg()
85 unsigned int rx_base = admaif->soc_data->rx_base; in tegra_admaif_wr_reg()
[all …]
/linux-5.10/Documentation/devicetree/bindings/rng/
Damlogic,meson-rng.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/rng/amlogic,meson-rng.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
16 - amlogic,meson-rng
18 reg:
24 clock-names:
26 - const: core
29 - compatible
[all …]
/linux-5.10/Documentation/devicetree/bindings/dma/
Dmv-xor-v2.txt4 - compatible: one of the following values:
5 "marvell,armada-7k-xor"
6 "marvell,xor-v2"
7 - reg: Should contain registers location and length (two sets)
10 - msi-parent: Phandle to the MSI-capable interrupt controller used for
14 - clocks: Optional reference to the clocks used by the XOR engine.
15 - clock-names: mandatory if there is a second clock, in this case the
16 name must be "core" for the first clock and "reg" for the second
23 compatible = "marvell,xor-v2";
24 reg = <0x400000 0x1000>,
[all …]
/linux-5.10/arch/arm64/boot/dts/qcom/
Dsc7180-idp.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
18 compatible = "qcom,sc7180-idp", "qcom,sc7180";
28 stdout-path = "serial0:115200n8";
40 /delete-node/ &hyp_mem;
41 /delete-node/ &xbl_mem;
42 /delete-node/ &aop_mem;
43 /delete-node/ &sec_apps_mem;
[all …]
Dpm660.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/input/linux-event-codes.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/spmi/spmi.h>
13 compatible = "qcom,pm660", "qcom,spmi-pmic";
14 reg = <0x0 SPMI_USID>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "qcom,pm8941-rtc";
20 reg = <0x6000>, <0x6100>;
[all …]
/linux-5.10/arch/arm64/boot/dts/toshiba/
Dtmpv7708-rm-mbrc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
15 compatible = "toshiba,tmpv7708-rm-mbrc", "toshiba,tmpv7708";
23 stdout-path = "serial0:115200n8";
29 reg = <0x0 0x80000000 0x0 0x30000000>;
36 clock-names = "apb_pclk";
42 clock-names = "apb_pclk";
/linux-5.10/arch/arm64/boot/dts/rockchip/
Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
14 stdout-path = "serial2:115200n8";
23 * - Rails that only connect to the EC (or devices that the EC talks to)
25 * - Rails _are_ included if the rails go to the AP even if the AP
34 * - The EC controls the enable and the EC always enables a rail as
36 * - The rails are actually connected to each other by a jumper and
41 ppvar_sys: ppvar-sys {
[all …]
/linux-5.10/drivers/clk/sunxi/
Dclk-a10-mod1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk-provider.h>
27 const char *clk_name = node->name; in sun4i_mod1_clk_setup()
28 void __iomem *reg; in sun4i_mod1_clk_setup() local
31 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); in sun4i_mod1_clk_setup()
32 if (IS_ERR(reg)) in sun4i_mod1_clk_setup()
43 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_mod1_clk_setup()
46 gate->reg = reg; in sun4i_mod1_clk_setup()
47 gate->bit_idx = SUN4I_MOD1_ENABLE; in sun4i_mod1_clk_setup()
48 gate->lock = &mod1_lock; in sun4i_mod1_clk_setup()
[all …]
/linux-5.10/Documentation/devicetree/bindings/clock/
Dhix5hd2-clock.txt8 - compatible: should be "hisilicon,hix5hd2-clock"
9 - reg: Address and length of the register set
10 - #clock-cells: Should be <1>
15 All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>.
19 compatible = "hisilicon,hix5hd2-clock";
20 reg = <0xf8a22000 0x1000>;
21 #clock-cells = <1>;
26 reg = <0xf8b00000 0x1000>;
29 clock-names = "apb_pclk";

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