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/linux-5.10/Documentation/devicetree/bindings/i2c/
Di2c-demux-pinctrl.txt1 Pinctrl-based I2C Bus DeMux
10 +-------------------------------+
12 | | +-----+ +-----+
13 | +------------+ | | dev | | dev |
14 | |I2C IP Core1|--\ | +-----+ +-----+
15 | +------------+ \-------+ | | |
16 | |Pinctrl|--|------+--------+
17 | +------------+ +-------+ |
18 | |I2C IP Core2|--/ |
19 | +------------+ |
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/linux-5.10/drivers/phy/mediatek/
Dphy-mtk-hdmi.c1 // SPDX-License-Identifier: GPL-2.0
7 #include "phy-mtk-hdmi.h"
21 void __iomem *reg = hdmi_phy->regs + offset; in mtk_hdmi_phy_clear_bits() local
24 tmp = readl(reg); in mtk_hdmi_phy_clear_bits()
26 writel(tmp, reg); in mtk_hdmi_phy_clear_bits()
32 void __iomem *reg = hdmi_phy->regs + offset; in mtk_hdmi_phy_set_bits() local
35 tmp = readl(reg); in mtk_hdmi_phy_set_bits()
37 writel(tmp, reg); in mtk_hdmi_phy_set_bits()
43 void __iomem *reg = hdmi_phy->regs + offset; in mtk_hdmi_phy_mask() local
46 tmp = readl(reg); in mtk_hdmi_phy_mask()
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/linux-5.10/arch/arm/boot/dts/
Dsun7i-a20-m3.dts6 * This file is dual-licensed: you can use it either under the terms
45 /dts-v1/;
46 #include "sun7i-a20.dtsi"
47 #include "sunxi-common-regulators.dtsi"
49 #include <dt-bindings/gpio/gpio.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
54 compatible = "mele,m3", "allwinner,sun7i-a20";
61 stdout-path = "serial0:115200n8";
65 compatible = "gpio-leds";
83 pinctrl-names = "default";
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Domap3-cm-t3x30.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Common support for CompuLab CM-T3x30 CoMs
6 #include "omap3-cm-t3x.dtsi"
11 cpu0-supply = <&vcc>;
16 compatible = "ti,omap-twl4030";
17 ti,model = "cm-t35";
26 pinctrl-single,pins = <
33 pinctrl-single,pins = <
50 #include "omap-gpmc-smsc911x.dtsi"
53 ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */
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Dgemini-rut1xx.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
19 reg = <0x00000000 0x8000000>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
30 button-setup {
31 debounce-interval = <100>;
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Dsun4i-a10-itead-iteaduino-plus.dts3 * Copyright 2015 - Marcus Cooper <codekipper@gmail.com>
5 * This file is dual-licensed: you can use it either under the terms
44 /dts-v1/;
45 #include "sun4i-a10.dtsi"
46 #include "sunxi-itead-core-common.dtsi"
50 compatible = "itead,iteaduino-plus-a10", "allwinner,sun4i-a10";
54 target-supply = <&reg_ahci_5v>;
59 pinctrl-names = "default";
60 pinctrl-0 = <&emac_pins>;
61 phy-handle = <&phy1>;
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Drk3288-veyron-jaq.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "rk3288-veyron-chromebook.dtsi"
11 #include "cros-ec-sbs.dtsi"
15 compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
16 "google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
17 "google,veyron-jaq-rev1", "google,veyron-jaq",
22 /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
23 brightness-levels = <0 8 255>;
24 num-interpolated-steps = <247>;
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Dqcom-apq8064-asus-nexus7-flo.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-apq8064-v2.0.dtsi"
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
8 compatible = "asus,nexus7-flo", "qcom,apq8064";
16 stdout-path = "serial0:115200n8";
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
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Dimx53-voipac-bsb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
7 #include "imx53-voipac-dmm-668.dtsi"
11 compatible = "fsl,imx53-voipac-sgtl5000",
12 "fsl,imx-audio-sgtl5000";
13 model = "imx53-voipac-sgtl5000";
14 ssi-controller = <&ssi2>;
15 audio-codec = <&sgtl5000>;
16 audio-routing =
18 mux-int-port = <2>;
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Dimx25-eukrea-mbimxsd25-baseboard.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include "imx25-eukrea-cpuimx25.dtsi"
14 compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
17 compatible = "gpio-keys";
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_gpiokeys>;
25 wakeup-source;
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Dimx6ull-colibri-nonwifi.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include "imx6ull-colibri.dtsi"
11 reg = <0x80000000 0x10000000>;
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2 &pinctrl_snvs_gpio3>;
/linux-5.10/Documentation/devicetree/bindings/usb/
Drenesas,usbhs.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas USBHS (HS-USB) controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - items:
16 - const: renesas,usbhs-r7s72100 # RZ/A1
17 - const: renesas,rza1-usbhs
19 - items:
20 - const: renesas,usbhs-r7s9210 # RZ/A2
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Ddwc3.txt3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
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/linux-5.10/Documentation/devicetree/bindings/media/i2c/
Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
17 - VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
18 - VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.
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Dov7251.txt1 * Omnivision 1/7.5-Inch B&W VGA CMOS Digital Image Sensor
3 The Omnivision OV7251 is a 1/7.5-Inch CMOS active pixel digital image sensor
8 - compatible: Value should be "ovti,ov7251".
9 - clocks: Reference to the xclk clock.
10 - clock-names: Should be "xclk".
11 - clock-frequency: Frequency of the xclk clock.
12 - enable-gpios: Chip enable GPIO. Polarity is GPIO_ACTIVE_HIGH. This corresponds
14 - vdddo-supply: Chip digital IO regulator.
15 - vdda-supply: Chip analog regulator.
16 - vddd-supply: Chip digital core regulator.
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/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h5-orangepi-zero-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 // Copyright (C) 2018 Hauke Mehrtens <hauke@hauke-m.de>
5 /dts-v1/;
6 #include "sun50i-h5.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/pinctrl/sun4i-a10.h>
14 compatible = "xunlong,orangepi-zero-plus", "allwinner,sun50i-h5";
17 compatible = "regulator-fixed";
18 regulator-name = "vcc3v3";
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Dsun50i-h6-orangepi-lite2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include "sun50i-h6-orangepi.dtsi"
8 compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6";
11 serial1 = &uart1; /* BT-UART */
15 compatible = "mmc-pwrseq-simple";
17 clock-names = "ext_clock";
18 reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
19 post-power-on-delay-ms = <200>;
24 vmmc-supply = <&reg_cldo2>;
25 vqmmc-supply = <&reg_bldo3>;
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Dsun50i-a64-pinephone.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "sun50i-a64.dtsi"
7 #include "sun50i-a64-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/pwm/pwm.h>
20 compatible = "pwm-backlight";
22 enable-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
27 stdout-path = "serial0:115200n8";
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/linux-5.10/arch/mips/boot/dts/img/
Dpistachio_marduk.dts1 // SPDX-License-Identifier: GPL-2.0-only
8 /dts-v1/;
14 compatible = "img,pistachio-marduk", "img,pistachio";
26 stdout-path = "serial1:115200";
31 reg = <0x00000000 0x10000000>;
34 reg_1v8: fixed-regulator {
35 compatible = "regulator-fixed";
36 regulator-name = "aux_adc_vref";
37 regulator-min-microvolt = <1800000>;
38 regulator-max-microvolt = <1800000>;
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/linux-5.10/sound/pci/oxygen/
Dxonar_dg_mixer.c1 // SPDX-License-Identifier: GPL-2.0-only
24 struct dg *data = chip->model_data; in output_select_apply()
26 data->cs4245_shadow[CS4245_SIGNAL_SEL] &= ~CS4245_A_OUT_SEL_MASK; in output_select_apply()
27 if (data->output_sel == PLAYBACK_DST_HP) { in output_select_apply()
30 } else if (data->output_sel == PLAYBACK_DST_HP_FP) { in output_select_apply()
36 data->cs4245_shadow[CS4245_SIGNAL_SEL] |= CS4245_A_OUT_SEL_DAC; in output_select_apply()
50 static const char *const names[3] = { in output_select_info() local
56 return snd_ctl_enum_info(info, 1, 3, names); in output_select_info()
62 struct oxygen *chip = ctl->private_data; in output_select_get()
63 struct dg *data = chip->model_data; in output_select_get()
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/linux-5.10/arch/arm64/boot/dts/rockchip/
Drk3399-rock-pi-4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/input/linux-event-codes.h>
9 #include <dt-bindings/pwm/pwm.h>
11 #include "rk3399-opp.dtsi"
15 stdout-path = "serial2:1500000n8";
18 clkin_gmac: external-gmac-clock {
19 compatible = "fixed-clock";
20 clock-frequency = <125000000>;
21 clock-output-names = "clkin_gmac";
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/linux-5.10/drivers/clk/renesas/
Dclk-sh73a0.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
21 void __iomem *reg; member
43 unsigned int reg; member
79 unsigned int shift, reg, width; in sh73a0_cpg_register_clock() local
86 u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3; in sh73a0_cpg_register_clock()
91 void __iomem *enable_reg = cpg->reg; in sh73a0_cpg_register_clock()
92 u32 enable_bit = name[3] - '0'; in sh73a0_cpg_register_clock()
109 return ERR_PTR(-EINVAL); in sh73a0_cpg_register_clock()
111 if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
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/linux-5.10/Documentation/devicetree/bindings/mmc/
Dhi3798cv200-dw-mshc.txt4 Read synopsys-dw-mshc.txt for more details
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon Hi3798CV200
13 - compatible: Should contain "hisilicon,hi3798cv200-dw-mshc".
14 - clocks: A list of phandle + clock-specifier pairs for the clocks listed
15 in clock-names.
16 - clock-names: Should contain the following:
17 "ciu" - The ciu clock described in synopsys-dw-mshc.txt.
18 "biu" - The biu clock described in synopsys-dw-mshc.txt.
19 "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling.
20 "ciu-drive" - Hi3798CV200 extended phase clock for ciu driving.
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/linux-5.10/Documentation/devicetree/bindings/power/
Damlogic,meson-gx-pwrc.txt7 ----------------
13 power-domain.yaml
16 ---------------------
19 - compatible: should be one of the following :
20 - "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
21 - "amlogic,meson-g12a-pwrc-vpu" for the Meson G12A SoCs
22 - #power-domain-cells: should be 0
23 - amlogic,hhi-sysctrl: phandle to the HHI sysctrl node
24 - resets: phandles to the reset lines needed for this power demain sequence
26 - clocks: from common clock binding: handle to VPU and VAPB clocks
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/linux-5.10/Documentation/devicetree/bindings/mux/
Dadi,adg792a.txt4 - compatible : "adi,adg792a" or "adi,adg792g"
5 - #mux-control-cells : <0> if parallel (the three muxes are bound together
8 * Standard mux-controller bindings as described in mux-controller.txt
11 - gpio-controller : if present, #gpio-cells below is required.
12 - #gpio-cells : should be <2>
13 - First cell is the GPO line number, i.e. 0 or 1
14 - Second cell is used to specify active high (0)
18 - idle-state : if present, array of states that the mux controllers will have
32 mux: mux-controller@50 {
34 reg = <0x50>;
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